PIC24FJ64GA004-IPT Datasheet, PDF (4/52 Pages) Microchip Technology – PIC24FJXXXGA0XX Flash Programming Specification

PIC24FJXXXGA0XX
Pin Diagrams
28-Pin PDIP, SSOP, SOIC
MCLR ¹
RA0 2
RA1 3
PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 4
PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1 5
RB2 6
RB3 7
VSS 8
RA2 9
RA3 10
RB4 11
RA4 12
VDD 13
PGD3/EMUD3/RP5/SDA1/CN27/PMD7/RB5 ¹⁴
28 VDD
27 ^VSS
26 ^RB15
25 ^RB14
24 RB13
23 ^RB12
22 ^{PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11}
21 PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10
20 ^VCAP/VDDCORE
19 DISVREG
18 RB9
17 RB8
16 RB7
15 PGC3/EMUC3/RP6/SCL1/CN24/PMD6/RB6
28-Pin QFN⁽¹⁾
PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0
PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1
RB2
RB3
VSS
RA2
RA3
28 27 26 25 24 23 22
1
21 RB13
2
20 RB12
3
19 PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11
4 ^{PIC24FJXXGA002} 18 PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10
5
17 VCAP/VDDCORE
6
16 DISVREG
7
15 RB9
8 9 10 11 12 13 14
Legend: RPx represents remappable peripheral pins.
Note 1: The bottom pad of QFN packages should be connected to VSS.
DS39768D-page 4
© 2008 Microchip Technology Inc.