PIC24FJ64GA004-IPT Datasheet, PDF (38/52 Pages) Microchip Technology – PIC24FJXXXGA0XX Flash Programming Specification

PIC24FJXXXGA0XX
5.2.8 PROGC COMMAND
15
12 11
87
0
Opcode
Length
Reserved
Addr_MSB
Addr_LS
Data
Field
Description
Opcode
Length
Reserved
Addr_MSB
Addr_LS
Data
4h
4h
0h
MSB of 24-bit destination address
Least Significant 16 bits of 24-bit
destination address
8-bit data word
The PROGC command instructs the programming
executive to program a single Device ID register
located at the specified memory address.
After the specified data word has been programmed to
code memory, the programming executive verifies the
programmed data against the data in the command.
Expected Response (2 words):
1400h
0002h
5.2.9 PROGP COMMAND
15
12 11
87
0
Opcode
Length
Reserved
Addr_MSB
Addr_LS
D_1
D_2
...
D_96
Field
Description
Opcode
5h
Length
63h
Reserved 0h
Addr_MSB MSB of 24-bit destination address
Addr_LS
Least Significant 16 bits of 24-bit
destination address
D_1
16-bit data word 1
D_2
16-bit data word 2
...
16-bit data word 3 through 95
D_96
16-bit data word 96
The PROGP command instructs the programming
executive to program one row of code memory, includ-
ing Configuration Words (64 instruction words), to the
specified memory address. Programming begins with
the row address specified in the command. The
destination address should be a multiple of 80h.
The data to program to memory, located in command
words, D_1 through D_96, must be arranged using the
packed instruction word format shown in Figure 5-5.
After all data has been programmed to code memory,
the programming executive verifies the programmed
data against the data in the command.
Expected Response (2 words):
1500h
0002h
Note: Refer to Table 2-3 for code memory size
information.
DS39768D-page 38
© 2008 Microchip Technology Inc.