PIC24HJ32GP302_11 Datasheet, PDF (363/368 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
PMD Module
Register Map............................................................... 46
PORTA
Register Map......................................................... 44, 45
PORTB
Register Map............................................................... 45
Power-on Reset (POR) ....................................................... 64
Power-Saving Features .................................................... 129
Clock Frequency and Switching................................ 129
Program Address Space ..................................................... 25
Construction................................................................ 49
Data Access from Program Memory
Using Program Space Visibility........................... 52
Data Access from Program Memory
Using Table Instructions ..................................... 51
Data Access from, Address Generation...................... 50
Memory Map ............................................................... 25
Table Read Instructions
TBLRDH ............................................................. 51
TBLRDL .............................................................. 51
Visibility Operation ...................................................... 52
Program Memory
Interrupt Vector ........................................................... 26
Organization................................................................ 26
Reset Vector ............................................................... 26
R
Reader Response ............................................................. 356
Register Map
CRC ............................................................................ 44
Dual Comparator......................................................... 44
Parallel Master/Slave Port .......................................... 43
Real-Time Clock and Calendar................................... 44
Registers
AD1CHS0 (ADC1 Input Channel 0 Select ................ 231
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select) ... 230
AD1CON1 (ADC1 Control 1) .................................... 225
AD1CON2 (ADC1 Control 2) .................................... 227
AD1CON3 (ADC1 Control 3) .................................... 228
AD1CON4 (ADC1 Control 4) .................................... 229
AD1CSSL (ADC1 Input Scan Select Low)................ 232
AD1PCFGL (ADC1 Port Configuration Low) ............ 232
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer)........... 207
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer)........... 208
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer)......... 208
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer)....... 209
CiCFG1 (ECAN Baud Rate Configuration 1) ............ 205
CiCFG2 (ECAN Baud Rate Configuration 2) ............ 206
CiCTRL1 (ECAN Control 1) ...................................... 198
CiCTRL2 (ECAN Control 2) ...................................... 199
CiEC (ECAN Transmit/Receive Error Count)............ 205
CiFCTRL (ECAN FIFO Control)................................ 201
CiFEN1 (ECAN Acceptance Filter Enable) ............... 207
CiFIFO (ECAN FIFO Status)..................................... 202
CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection)..... 211,
212
CiINTE (ECAN Interrupt Enable) .............................. 204
CiINTF (ECAN Interrupt Flag)................................... 203
CiRXFnEID (ECAN Acceptance Filter n
Extended Identifier)........................................... 211
CiRXFnSID (ECAN Acceptance Filter n
Standard Identifier) ........................................... 210
CiRXFUL1 (ECAN Receive Buffer Full 1) ................. 214
CiRXFUL2 (ECAN Receive Buffer Full 2) ................. 214
CiRXMnEID (ECAN Acceptance Filter Mask n
Extended Identifier)........................................... 213
CiRXMnSID (ECAN Acceptance Filter Mask n
Standard Identifier) ........................................... 213
CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 215
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 215
CiTRBnSID (ECAN Buffer n Standard Identifier)..... 217,
218, 220
CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 216
CiVEC (ECAN Interrupt Code) ................................. 200
CLKDIV (Clock Divisor) ............................................ 125
CORCON (Core Control)...................................... 23, 73
DMACS0 (DMA Controller Status 0) ........................ 114
DMACS1 (DMA Controller Status 1) ........................ 116
DMAxCNT (DMA Channel x Transfer Count)........... 113
DMAxCON (DMA Channel x Control)....................... 110
DMAxPAD (DMA Channel x Peripheral Address) .... 113
DMAxREQ (DMA Channel x IRQ Select) ................. 111
DMAxSTA (DMA Channel x RAM Start Address A) . 112
DMAxSTB (DMA Channel x RAM Start Address B) . 112
DSADR (Most Recent DMA RAM Address) ............. 117
I2CxCON (I2Cx Control)........................................... 183
I2CxMSK (I2Cx Slave Mode Address Mask)............ 187
I2CxSTAT (I2Cx Status) ........................................... 185
IFS0 (Interrupt Flag Status 0) ............................... 76, 83
IFS1 (Interrupt Flag Status 1) ............................... 78, 85
IFS2 (Interrupt Flag Status 2) ............................... 80, 87
IFS3 (Interrupt Flag Status 3) ............................... 81, 88
IFS4 (Interrupt Flag Status 4) ............................... 82, 89
INTCON1 (Interrupt Control 1) ................................... 74
INTCON2 (Interrupt Control 2) ................................... 75
INTTREG Interrupt Control and Status Register ...... 104
IPC0 (Interrupt Priority Control 0) ............................... 90
IPC1 (Interrupt Priority Control 1) ............................... 91
IPC11 (Interrupt Priority Control 11) ......................... 100
IPC15 (Interrupt Priority Control 15) ......................... 101
IPC16 (Interrupt Priority Control 16) ......................... 102
IPC17 (Interrupt Priority Control 17) ......................... 103
IPC2 (Interrupt Priority Control 2) ............................... 92
IPC3 (Interrupt Priority Control 3) ............................... 93
IPC4 (Interrupt Priority Control 4) ............................... 94
IPC5 (Interrupt Priority Control 5) ............................... 95
IPC6 (Interrupt Priority Control 6) ............................... 96
IPC7 (Interrupt Priority Control 7) ............................... 97
IPC8 (Interrupt Priority Control 8) ............................... 98
IPC9 (Interrupt Priority Control 9) ............................... 99
NVMCON (Flash Memory Control)............................. 55
NVMKEY (Nonvolatile Memory Key) .......................... 56
OCxCON (Output Compare x Control) ..................... 173
OSCCON (Oscillator Control)................................... 123
OSCTUN (FRC Oscillator Tuning)............................ 127
PLLFBD (PLL Feedback Divisor) ............................. 126
PMD1 (Peripheral Module Disable
Control Register 1) ........................................... 131
PMD2 (Peripheral Module Disable
Control Register 2) ........................................... 132
PMD3 (Peripheral Module Disable
Control Register 3) ........................................... 133
RCON (Reset Control)................................................ 60
SPIxCON1 (SPIx Control 1) ..................................... 177
SPIxCON2 (SPIx Control 2) ..................................... 179
SPIxSTAT (SPIx Status and Control) ....................... 176
SR (CPU Status) .................................................. 22, 72
T1CON (Timer1 Control) .......................................... 162
TCxCON (Input Capture x Control) .......................... 170
TxCON (Type B Time Base Control) ........................ 166
TyCON (Type C Time Base Control)........................ 167
UxMODE (UARTx Mode) ......................................... 190
UxSTA (UARTx Status and Control) ........................ 192
Reset
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DS70293E-page 363