PIC24HJ32GP302_11 Datasheet, PDF (106/368 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
The DMA controller features eight identical data
transfer channels.
Each channel has its own set of control and status
registers. Each DMA channel can be configured to
copy data either from buffers stored in dual port DMA
RAM to peripheral SFRs, or from peripheral SFRs to
buffers in DMA RAM.
The DMA controller supports the following features:
• Eight DMA channels
• Register Indirect with Post-increment Addressing
mode
• Register Indirect without Post-increment
Addressing mode
• Peripheral Indirect Addressing mode (peripheral
generates destination address)
• CPU interrupt after half or full block transfer
complete
• Byte or word transfers
• Fixed priority channel arbitration
• Manual (software) or Automatic (peripheral DMA
requests) transfer initiation
• One-Shot or Auto-Repeat block transfer modes
• Ping-Pong mode (automatic switch between two
DPSRAM start addresses after each block
transfer complete)
• DMA request for each channel can be selected
from any supported interrupt source
• Debug support features
For each DMA channel, a DMA interrupt request is
generated when a block transfer is complete.
Alternatively, an interrupt can be generated when half of
the block has been filled.
FIGURE 8-1:
SRAM
TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS
Peripheral Indirect Address
DMA Controller
DMA RAM
PORT 1 PORT 2
DMA
Channels
DMA
Ready
Peripheral 3
CPU DMA
SRAM X-Bus
DMA DS Bus
CPU Peripheral DS Bus
CPU
Non-DMA
Ready
Peripheral
Note: CPU and DMA address buses are not shown for clarity.
CPU DMA
DMA
Ready
Peripheral 1
CPU DMA
DMA
Ready
Peripheral 2
DS70293E-page 106
© 2011 Microchip Technology Inc.