71M6533 Datasheet, PDF (99/132 Pages) Teridian Semiconductor Corporation – Energy Meter IC

FDS_6533_6534_004
71M6533/G/H and 71M6534/H Data Sheet
The EXT_TEMP bit enables temperature compensation mode:
• When EXT_TEMP = 0 (internal compensation), the CE will control the gain using GAIN_ADJ (see
Table 59) based on PPMC, PPMC2 and TEMP_X, the difference between die temperature and the
reference / calibration temperature TEMP_NOM. Since PPMC and PPMC2 reflect the typical behavior
of the reference voltage over temperature, the internal temperature compensation eliminates the effects
of temperature-related errors of VREF only.
• When EXT_TEMP = 1 (external compensation), the MPU is allowed to control the CE gain using
GAIN_ADJ, based on any algorithm implemented in MPU code.
The 71M6533 Demo Code creep function halts both internal and external pulse generation.
The FREQSEL1 and FREQSEL0 bits select the phase used to control the CE-internal PLL. CE accuracy
depends on the channel selected by the FREQSEL1 and FREQSEL0 bits receiving a clean voltage signal.
CECONFIG
[bit]
Name
[20]
SAG_MASK2
[19]
SAG_MASK1
[18]
SAG_MASK0
[17]
SAG_INT
[16]
EXT_TEMP
[15:8]
SAG_CNT
[7]
FREQSEL1
[6]
FREQSEL0
[5]
EXT_PULSE
[4]
IC_SHUNT
[3]
IB_SHUNT
[2]
IA_SHUNT
Table 58: CECONFIG Bit Definitions
Default Description
0
0
0
0
0
80
(0x50)
0
0
1
0
0
0
When 1, enables sag interrupt based on phase C.
When 1, enables sag interrupt based on phase B.
When 1, enables sag interrupt based on phase A.
If more than one sag mask is set, a sag interrupt will only be
generated when all phases enabled for the interrupt sag.
When 1, enables the sag interrupt to be output on the
YPULSE/DIO9 pin (see Section 1.5.7).
When set, enables the control of GAIN_ADJ by the MPU.
When 0, enables the control of GAIN_ADJ by the CE.
The number of consecutive voltage samples below SAG_THR
before a sag alarm is declared. The maximum value is 255.
SAG_THR is at address 0x24.
The combination of FREQSEL1 and FEQSEL0 selects the phase
to be used for the frequency monitor, the phase-to-phase lag
calculation,the zero crossing counter (MAINEDGE_X), and the
F0 bit (CESTATUS[28]).
FREQ FREQ
SEL1 SEL0
Phase
Selected
Phases Used for Voltage
Phase Lag Calculation
PH_A to B_X PH_A to C_X
0
0
A
A-B
A-C
0
1
B
B-C
B-A
1
0
C
C-A
C-B
1
1
Not allowed
When zero, causes the pulse generators to respond to internal
data (WPULSE = WSUM_X, RPULSE = VARSUM_X).
Otherwise, the generators respond to values the MPU places
in APULSEW and APULSER.
When 1, the current gain of channel C is increased by 8. The
gain factor controlled by In_SHUNT is referred to as In_8
throughout this document.
When 1, the current gain of channel B is increased by 8.
When 1, the current gain of channel A is increased by 8.
Rev 2
99