71M6533 Datasheet, PDF (53/132 Pages) Teridian Semiconductor Corporation – Energy Meter IC

FDS_6533_6534_004
71M6533/G/H and 71M6534/H Data Sheet
SERIAL READ
8 bit CMD
16 bit Address
DATA[ADDR]
DATA[ADDR+1]
PCSZ
0
PSCK
(From Host) PSDI x C7 C6 C5
(From 653X) PSDO
78
C0 A15 A14
HI Z
23 24
A1 A0 x
D7 D6
Extended Read . . .
31 32
39
D1 D0 D7 D6
D1 D0
SERIAL WRITE
8 bit CMD
16 bit Address
DATA[ADDR]
DATA[ADDR+1]
PCSZ
0
PSCK
78
23 24
Extended Write . . .
31 32
39
(From Host) PSDI x C7 C6 C5
(From 653X) PSDO
C0 A15 A14
A1 A0 D7 D6
HI Z
D1 D0 D7 D6
Figure 16: SPI Slave Port: Typical Read and Write Operations
D1 D0 x
SFR locations, i.e. the control registers internal to the 71M653x MPU, are not accessible via the SPI port.
In cases where these registers have to be accessed, for example to control DIO pins, a protocol that uses
the MPU has to be used for read and write operations involving the SFRs.
1.5.12 Hardware Watchdog Timer
An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6533/71M6534. It
uses the RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every
V1
1.5 seconds. When not refreshed on time, the WDT overflows and the
part is reset as if the RESET pin were pulled high, except that the I/O
V3P3
V3P3 - 10mV
WDT dis-
abled
RAM bits will be in the same state as after a wake-up from SLEEP or LCD
modes (see the I/O RAM description in Section 5.2 for a list of I/O RAM bit
states after RESET and wake-up). 4100 oscillator cycles (or 125 ms) after
V3P3 -
the WDT overflow, the MPU will be launched from program address
400mV
0x0000.
Normal
operation,
WDT
enabled
A status bit, WD_OVF, is set when the WDT overflow occurs. This bit is
preserved in LCD mode (not in SLEEP mode) and can be read by the
MPU when WAKE rises to determine if the part is initializing after a WDT
VBIAS
overflow event or after a power-up. After it is read, the MPU firmware
must clear WD_OVF. The WD_OVF bit is also cleared by the RESET pin.
Battery
modes
There is no internal digital state that deactivates the WDT. The WDT can
be disabled by tying the V1 pin to V3P3 (see Figure 17). Of course, this
also deactivates V1 power fault detection. Since there is no method in
firmware to disable the crystal oscillator or the WDT, it is guaranteed that
whatever state the part might find itself in, upon watchdog overflow, the
part will be reset to a known state.
0V
Figure 17: Functions Defined by V1
Asserting ICE_E will also deactivate the WDT. This is the only method that will work in BROWNOUT mode.
In normal operation, the WDT is reset by periodically writing a one to the WDT_RST bit. The watchdog timer
is also reset when the internal signal WAKE=0 (see Section 2.5 Wake Up Behavior).
Rev 2
53