71M6533 Datasheet, PDF (87/132 Pages) Teridian Semiconductor Corporation – Energy Meter IC

FDS_6533_6534_004
GP0
20C0
0
…
…
…
GP7
20C7
0
IE_FWCOL0
SFR E8[2]
0
IE_FWCOL1
SFR E8[3]
0
IE_PB
SFR E8[4]
0
IE_PLLRISE
SFR E8[6]
0
IE_PLLFALL
SFR E8[7]
0
IEN_SPI
20B0[4]
IEN_WD_NROVF 20B0[0]
0
IE_XFER
SFR E8[0]
0
IE_RTC
SFR E8[1]
0
IE_WAKE
SFR E8[5]
0
INTBITS
SFR F8[6:0] –
LCD_BITMAP
[31:24]
2023[7:0]
0
LCD_BITMAP
[39:32]
2024[7:0]
0
LCD_BITMAP
[47:40]
2025[7:0]
0
LCD_BITMAP
[50:48]
2026[2:0]
0
71M6533/G/H and 71M6534/H Data Sheet
NV
Non-volatile general-purpose registers powered by the RTC supply. These registers
… R/W maintain their value in all power modes, but will be cleared on reset. The values of
NV
GP0…GP7 will be undefined if VBAT drops below the minimum value.
0 R/W Interrupt flags for the Firmware Collision Interrupt. See the Flash Memory section for
0 R/W details.
PB flag. Indicates that a rising edge occurred on PB. Firmware must write a zero to
–
R/W
this bit to clear it. The bit is also cleared when the MPU requests SLEEP or LCD
mode. On bootup, the MPU can read this bit to determine if the part was woken with
the PB DIO0[0].
Indicates that the MPU was woken or interrupted (INT4) by system power becoming
0 R/W available, or more precisely, by PLL_OK rising. The firmware must write a zero to this
bit to clear it.
Indicates that the MPU has entered BROWNOUT mode because system power has
0
R/W
become unavailable (INT4), or more precisely, because PLL_OK fell. This bit will not
be set if the part wakes into BROWNOUT mode because of PB or the WAKE timer.
The firmware must write a zero to this bit to clear it.
R/W SPI interrupt enable.
0 R/W Active high watchdog near overflow interrupt enable.
0
0
R/W
Interrupt flags. These flags monitor the XFER_BUSY interrupt and the RTC_1SEC
interrupt. The flags are set by hardware.
–
R/W
Indicates that the MPU was awakened by the autowake timer. This bit is typically read
by the MPU on bootup. The firmware must write a zero to this bit to clear it.
Interrupt inputs. The MPU may read these bits to see the status of external interrupts
– R/W INT0, INT1 up to INT6. These bits do not have any memory and are primarily intended
for debug use.
L
R/W
Configuration for DIO11/SEG31 through DIO4/SEG24. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin.
Configuration for DIO19/SEG39 through DIO12/SEG32. LCD_BITMAP[32] ,
L
R/W
corresponding to DIO12/SEG32, is only applicable to the 71M6534. Unused bits
should be set to zero.
1 = LCD pin, 0 = DIO pin.
Configuration for DIO27/SEG47 through DIO20/SEG40. LCD_BITMAP[42],
L
R/W
corresponding to DIO22/SEG42, is only applicable to the 71M6534. Unused bits should
be set to zero.
1 = LCD pin, 0 = DIO pin.
Configuration for DIO30/SEG50 through DIO28/SEG48. LCD_BITMAP[48],
L
R/W
corresponding to DIO28/SEG48, is only applicable to the 71M6534. Unused bits should
be set to zero.
1 = LCD pin, 0 = DIO pin.
Rev 2
87