71M6533 Datasheet, PDF (17/132 Pages) Teridian Semiconductor Corporation – Energy Meter IC

FDS_6533_6534_004
71M6533/G/H and 71M6534/H Data Sheet
The Data RAM is 32 bits wide and uses an external multiplexer so as to appear byte-wide to the MPU.
The Data RAM hardware will convert an MPU byte write operation into a read-modify-write operation that
requires two Data RAM accesses. The second access is guaranteed to be available because the MPU
cannot access the XRAM on two consecutive instructions unless it is using the same address.
In addition to the reduction of wait states, this arrangement permits the MPU to easily use unneeded CE
data memory. Likewise, the amount of memory the CE uses is not limited by the size of a dedicated CE
data RAM.
1.3.5 CE Functional Overview
The ADC processes one sample per channel per multiplexer cycle. Figure 5 shows the timing of the
samples taken during one multiplexer cycle (phases A, B, and C being processed). During an ALT
multiplexer sequence, missing samples are filled in by the CE.
The number of samples processed during one accumulation cycle is controlled by PRE_SAMPS[1:0] (I/O
RAM 0x2001[7:6]) and SUM_CYCLES[5:0] (I/O RAM 0x2001[5:0]). The integration time for each energy
output is:
PRE_SAMPS[1:0] * SUM_CYCLES[5:0] / 2520.6, where 2520.6 is the sample rate in Hz
For example, PRE_SAMPS[1:0] = 42 and SUM_CYCLES[5:0] = 50 will establish 2100 samples per accumulation
cycle. PRE_SAMPS[1:0] = 100 and SUM_CYCLES[5:0] = 21 will result in the exact same accumulation
cycle of 2100 samples or 833 ms. After an accumulation cycle is completed, the XFER_BUSY interrupt
signals to the MPU that accumulated data are available.
1/2520.6Hz = 397µs
IB
B
VB
IC
2/32768Hz =
61.04µs
A
IA
VC
VA
C
13/32768Hz = 397µs
per mux cycle
Figure 5: Samples from Multiplexer Cycle
The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each
multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the MPU.
Rev 2
17