English
Language : 

71M6533 Datasheet, PDF (15/132 Pages) Teridian Semiconductor Corporation – Energy Meter IC
FDS_6533_6534_004
71M6533/G/H and 71M6534/H Data Sheet
Table 4: XRAM Locations for ADC Results
Address (HEX)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07 – 0x09
0x0A
0x0B
Name
IA
VA
IB
VB
IC
VC
ID
–
TEMP
VBAT
Description
Phase A current
Phase A voltage
Phase B current
Phase B voltage
Phase C current
Phase C voltage
Neutral current
Not used
Temperature
Battery Voltage
The CE is aided by support hardware to facilitate implementation of equations, pulse counters, and
accumulators. This hardware is controlled through I/O RAM locations EQU[2:0] (equation assist), the
DIO_PV and DIO_PW (pulse count assist) bits, and PRE_SAMPS[1:0] and SUM_CYCLES[5:0] (accumulation
assist).
PRE_SAMPS[1:0] and SUM_CYCLES[5:0] support a dual-level accumulation scheme where the first
accumulator accumulates results from PRE_SAMPS[1:0] samples and the second accumulator accumulates
up to SUM_CYCLES[5:0] of the first accumulator results. The integration time for each energy output is
PRE_SAMPS[1:0] * SUM_CYCLES[5:0] / 2520.6 (with MUX_DIV[3:0] = 6). CE hardware issues the
XFER_BUSY interrupt when the accumulation is complete.
1.3.1 Meter Equations
The 71M6533 and 71M6534 provide hardware assistance to the CE in order to support various meter
equations. This assistance is controlled through the I/O RAM field EQU[2:0] (equation assist). The
Compute Engine (CE) firmware for industrial configurations can implement the equations listed in Table 5.
EQU[2:0] specifies the equation to be used based on the meter configuration and on the number of phases
used for metering.
Table 5: Inputs Selected in Regular and Alternate Multiplexer Cycles
EQU[2:0] Description
1 element, 2 W,
0 1φ with neutral
current sense
1 1 element, 3 W, 1φ
2
2 element, 3 W,
3φ Delta
3
2 element, 4 W,
3φ Delta
4
2 element, 4 W,
3φ Wye
5
3 element, 4 W,
3φ Wye
Wh and VARh formula
Element Element Element
0
1
2
VA ∙ IA VA ∙ IB
N/A
VA(IA-IB)/2 N/A
N/A
VA ∙ IA VB ∙ IB
N/A
VA(IA-IB)/2 N/A
VC ∙IC
VA(IA-IB)/2 VB(IC-IB)/2 N/A
VA ∙ IA VB ∙ IB VC ∙ IC
Mux
Sequence
ALT Mux
Sequence
Sequence is
programmable
with
SLOTn_SEL[3:0]
Sequence is
programmable with
SLOTn_ALTSEL[3:0]
Not all CE codes support all equations.
Rev 2
15