71M6533 Datasheet, PDF (16/132 Pages) Teridian Semiconductor Corporation – Energy Meter IC

71M6533/G/H and 71M6534/H Data Sheet
FDS_6533_6534_004
1.3.2 Real-Time Monitor
The CE contains a Real-Time Monitor (RTM), which can be programmed to monitor four selectable XRAM
locations at full sample rate. The four monitored locations are serially output to the TMUXOUT pin via the
digital output multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled
with the RTM_E bit. The RTM output is clocked by CKTEST (pin SEG19/CKTEST), with the clock output
enabled by setting CKOUT_E = 1. Each RTM word is clocked out in 35 cycles and contains a leading flag
bit. See Figure 20 for the RTM output format. RTM is low when not in use.
1.3.3 Pulse Generators
The 71M6533 and 71M6534 provide four pulse generators, RPULSE, WPULSE, XPULSE and YPULSE,
as well as hardware support for the RPULSE and WPULSE pulse generators. The pulse generators can
be used to output CE status indicators, SAG for example, to DIO pins.
The polarity of the pulses may be inverted with PLS_INV bit. When this bit is set, the pulses are active
high, rather than the more usual active low. PLS_INV inverts all the pulse outputs.
XPULSE and YPULSE
Pulses generated by the CE may be exported to the XPULSE and YPULSE pulse outputs. Pins DIO8
and DIO9 are used for these pulses. Generally, the XPULSE and YPULSE outputs are updated once on
each pass of the CE code, resulting in a pulse frequency up to a maximum of 1260Hz (assuming a MUX
frame is 13 CK32 cycles).
Standard CE code permits the selection of either an energy indication or signaling of a sag event for the
YPULSE output. This method is faster than checking the sag bits by the MPU at every CE_BUSY interrupt.
See Section 5.3 CE Interface Description for details.
RPULSE and WPULSE
During each CE code pass, the hardware stores exported WPULSE and RPULSE sign bits in an 8-bit
FIFO and outputs them at a specified interval. This permits the CE code to calculate the RPULSE and
WPULSE outputs at the beginning of its code pass and to rely on hardware to spread them over the MUX
frame. The FIFO is reset at the beginning of each MUX frame. The PLS_INTERVAL register controls the
delay to the first pulse update and the interval between subsequent updates. The LSB of this register is
equivalent to 4 CK_FIR cycles. If zero, the FIFO is deactivated and the pulse outputs are updated
immediately. Thus, NINTERVAL is 4 * PLS_INTERVAL.
Since the FIFO resets at the beginning of each MUX frame, the user must specify PLS_INTERVAL so that
all of the pulse updates are output before the MUX frame completes. For instance, if the CE code outputs
6 updates per MUX interval, and if the MUX interval is 1950 cycles long, the ideal value for the interval is
1950/6/4 = 81.25. If PLS_INTERVAL = 82, the fifth output will occur too late and be lost. In this case, the
proper value for PLS_INTERVAL is 81.
Hardware also provides a maximum pulse width feature. The PLS_MAXWIDTH register selects a maximum
negative pulse width to be Nmax updates according to the formula: Nmax = (2 * PLS_MAXWIDTH + 1). If
PLS_MAXWIDTH = 255, no width checking is performed.
The WPULSE and RPULSE pulse generator outputs are available on DIO6 and DIO7, respectively. They
can also be output on OPT_TX (see OPT_TXE[1:0] for details).
1.3.4 Data RAM (XRAM)
The CE and MPU use a single general-purpose Data RAM (also referred to as XRAM). The Data RAM is
1024 32-bit words, shared between the CE and the MPU using a time-multiplex method. This reduces
MPU wait states when accessing CE data. When the MPU and CE are clocking at maximum frequency
(10 MHz), the DRAM will make up to four accesses during each 100 ns interval. These consist of two
MPU accesses, one CE access and one SPI access.
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