71M6533 Datasheet, PDF (39/132 Pages) Teridian Semiconductor Corporation – Energy Meter IC

FDS_6533_6534_004
71M6533/G/H and 71M6534/H Data Sheet
The second rate adjustment is a digital rate adjust using PREG[16:0] and QREG[1:0], which can be used
to adjust the clock rate up to ± 988 ppm, with a resolution of 3.8 ppm. Updates must occur after a one
second interrupt, and must finish before the next one second boundary. The rate adjustment will be
implemented starting at the next one-second boundary. Since the LSB results in an adjustment every
four seconds, the frequency should be measured over an interval that is a multiple of four seconds.
To adjust the clock rate using the digital rate adjust, the appropriate values must be written to PREG[16:0]
and QREG[1:0]. The default frequency is 32,768 RTCLK cycles per second. To shift the clock frequency
by ∆ ppm, calculate PREG[16:0] and QREG[1:0] using the following equation:
4 ⋅ PREG
+ QREG
=
floor

32768 ⋅ 8
1 + ∆ ⋅10^−6
+
0.5

For example, for a shift of -988 ppm, 4⋅PREG + QREG = 262403 = 0x40103. PREG[16:0] = 0x10040, and
QREG[1:0] = 0x03. The default values of PREG[16:0] and QREG[1:0], corresponding to zero adjustment,
are 0x10000 and 0x0, respectively.
The RTC timing may be observed on the TMUXOUT pin by setting TMUX[4:0] to 0x10 or 0x11.
Default values for RTCA_ADJ[6:0], PREG[16:0] and QREG[1:0] should be nominal values, at the
center of the adjustment range. Uncalibrated extreme values (zero, for example) can cause incorrect
operation.
If the crystal temperature coefficient is known, the MPU can integrate temperature and correct the RTC
time as necessary.
Both RTCA_ADJ[6:0] and PREG[16:0]/QREG[1:0] are non-volatile registers, i.e. their values will be
preserved in BROWNOUT, SLEEP and LCD modes. However, the digital correction controlled by the
PREG[16:0]/QREG[1:0] registers is not operational in SLEEP mode.
The digital adjustment using PREG[16:0] and QREG[1:0] is preferred over the analog adjustment using
RTCA_ADJ: The digital adjustment is more repeatable and has a wider range.
The sub-second register of the RTC, SUBSEC, can be read by the MPU after the one-second interrupt and
before reaching the next one second boundary. SUBSEC contains the count remaining, in 1/256 second
nominal clock periods, until the next one-second boundary. When the RST_SUBSEC bit is written, the
SUBSEC counter is restarted. Reading and resetting the sub-second counter can be used as part of an
algorithm to accurately set the RTC.
When setting the RTC_SEC register, it is important to take into account that the associated write operation
will be performed only in the next second boundary.
1.5.4 Temperature Sensor
The device includes an on-chip temperature sensor for determining the temperature of the bandgap
reference. If automatic temperature measurement is not performed by selecting CHOP_E[1:0] = 00, the
MPU may request an alternate multiplexer frame containing the temperature sensor output by asserting
MUX_ALT. The primary use of the temperature data is to determine the magnitude of compensation
required to offset the thermal drift in the system (see Section 3.5 Temperature Compensation).
1.5.5 Physical Memory
Flash Memory
The device includes 128 KB (71M6533/H, 71M6534) or 256 KB (71M6533G, 71M6534H) of on-chip flash
memory. The flash memory primarily contains MPU and CE program code. It also contains images of
the CE and MPU data in RAM as well as of I/O RAM. On power-up, before enabling the CE, the MPU
copies these images to their respective locations.
Rev 2
39