MAX1441 Datasheet, PDF (39/41 Pages) Maxim Integrated Products – Automotive, Two-Channel Proximity and Touch Sensor

Automotive, Two-Channel Proximity and
Touch Sensor
JTAG Port
The device supports a TAP and TAP controller for
communication with a bus master that can be either an
automatic test equipment or a component that interfaces
to a higher level test bus as part of a complete system.
The communication operates across a 4-wire serial
interface from a dedicated TAP, which is compatible to
the JTAG IEEE^M Standard 1149. The TAP is a general-
purpose port, which allows access to many debug and test
functions built into the core.
For detailed information on the TAP and TAP
controller, refer to IEEE Standard 1149.1 IEEE Standard
Test Access Port and Boundary-Scan Architecture.
Bootstrap Loader Mode
Internal nonvolatile memory can be initialized by the
bootstrap loader in bootstrap loader mode. The boot-
strap loader mode is enabled by an external host device
using the TAP in the system programming instruction.
The system programming function is supported using
the system programming buffer (SPB):
1) SPB.0–System programming enable (SPE)
When it is set, the bootstrap loader program is
activated to perform a bootstrap loader function.
When it is cleared, the reset vector forces the IP to
8000h and starts normal user-program execution.
2) SPB.2:1–Programming source select (PSS[1:0])
These bits allow the host to select programming inter-
face sources:
PSS1
0
0
1
1
PSS0
0
1
0
1
PROGRAMMING SOURCE
JTAG
Reserved
Reserved
Reserved
User Mode
User applications are executed in user mode. In user
mode, the processor can execute program routines in any
memory segments. Normally, data is loaded and stored
from/to the data memory. The device contains three mem-
ory segments among the program and the data spaces:
• Program segment
• Data segment
• Utility ROM segment
Password-Protected Access
Some applications require preventive measures to pro-
tect against simple access and viewing of program code
memory. To address this need for code protection, the
device grants full access to in-system programming
or in-circuit debugging utilities only after a password
has been supplied. The password is defined as the 16
words of physical program memory at addresses 0010h
to 001Fh. Note that using these memory locations for
a password does not exclude their usage for general
code space if a unique password is not needed. Also, if
addresses 0010h to 001Fh contain all zeros or all FFFFs,
the password function is effectively disabled and a pass-
word is not needed to gain access.
A single password lock bit (PWL) is implemented in the
SC register. When the PWL is set to 1, a password is
required to access the ROM loader utilities, which sup-
port read/write accessing of internal memory and debug
functions. When PWL is cleared to 0, these utilities are fully
accessible through the utility ROM without a password.
The PWL bit defaults to 1 by a POR. To access the
ROM utilities, a correct password is needed; otherwise,
access of ROM utilities is denied. Once the correct
password has been supplied by the user, the ROM utility
clears the password lock. The PWL remains clear until
one of the following occurs:
• A power-on reset
OR
• Set to logic 1 by user software.
A password can be entered:
Entering Password
• Using the interface established by the PSS1 and
PSS0 bits in system programming when the SPE bit
is set to logic 1; the ROM loader must establish a
suitable protocol for that interface to recognize the
multibyte password.
OR
• Through the TAP interface directly in debug mode or
test mode by issuing a password-unlock command;
this command requires 32 follow-on transfer cycles,
each containing a byte value compared with the
password.
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