MAX1441 Datasheet, PDF (36/41 Pages) Maxim Integrated Products – Automotive, Two-Channel Proximity and Touch Sensor

Automotive, Two-Channel Proximity and
Touch Sensor
Table 13. Watchdog Timer Timeout Interval
WD[1:0]
00
01
10
11
TIMEOUT COUNT
16384
32768
65536
131072
TIMEOUT (s)
0.5
1.0
2.0
4.0
Watchdog Timer
The watchdog timer is clocked by the internal 32kHz
oscillator (Table 13). All timing reference for the watch-
dog is based on the 32kHz.
In addition, the watchdog is disabled in debug mode
and when SPE is set to 1. Clock to the watchdog is gated
off in the conditions mentioned in the Clock Sources
section.
Startup Timer
An independent startup timer (X-dog timer) functions:
• When the device is first powered up (POR)
• Exis from stop mode
The X-dog counter is used to count eight oscillator
cycles of the 5MHz after the power supply is stable.
The power supply is stable after three-to-four 32kHz
oscillator cycles.
The AFE circuit is released at least one 32kHz oscillator
cycle before the CPU to allow for the 5MHz clock startup
to properly occur.
The X-dog timer is active only for startup count; during
normal operation, it is completely shut off.
Idle Mode
The device supports idle mode. Idle mode suspends
the processor by holding the instruction pointer (IP) in a
static state. No instructions are fetched and no process-
ing occurs. Setting the IDLE bit in the SC register to logic
1 invokes the idle mode. The instruction that executes
this step is the last instruction prior to freezing the
program counter. Once in idle mode, all resources are
preserved and all clocks remain active with the enabled
peripherals. The power monitor continues to work, so the
processor can exit the idle state using any of the inter-
rupt sources that are enabled. The IDLE bit is cleared
automatically once the idle state is exited, allowing the
processor to execute the instruction that immediately
follows the instruction that sets the IDLE bit.
Resetting the processor also removes the idle mode.
Reset places the processor in a reset state and clears
the IDLE bit.
Stop Mode
The stop mode disables all circuits within the
processor, unless explicitly stated otherwise. All
microcontroller system clocks, timers, and serial
communication are stopped and no processing is pos-
sible. However, the AFE can be left in the standby mode
and remain functional.
Once in stop mode, the CPU is in a static state. Its power
consumption is mostly limited by the leakage current.
Stop mode is invoked by setting the STOP bit to logic 1.
The processor enters the stop mode on the instruction
that sets the STOP bit. Entering the stop mode does not
affect the setting of the clock control bits. This allows
the system to return to its original operating frequency
following the stop mode removal, except if the removal is
caused by RST or a power loss, which resets the clock
generation to its default condition.
The processor can exit stop mode by:
• Any of the external interrupts that are enabled.
• External reset using the RST pin.
• Timer interrupt.
• Watchdog timeout.
• AFE interrupts that are enabled.
When the stop mode is removed, the device executes
the following procedure:
1) Remove clock gating of internal 5MHz.
2) Reset the warm-up counter.
3) Wait for Flash to power up (about 10Fs).
4) Allow the required warm-up delay of eight oscillator
cycles of the 5MHz input.
5) Resume normal operation.
During stop mode, the following peripherals can be
operational:
• Timer (TMREN = 1)
• Watchdog timer (WDCN.EWDI = 1)
• AFE
Reset Conditions
The device has four ways of entering a reset state:
• Power-on reset
• Watchdog timer reset
• External reset
• Internal system reset
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