MAX1441 Datasheet, PDF (14/41 Pages) Maxim Integrated Products – Automotive, Two-Channel Proximity and Touch Sensor

Automotive, Two-Channel Proximity and
Touch Sensor
Table 5. Special-Purpose Register Bit Description (continued)
REGISTER
PSF (04h, 08h)
Initialization
Read/Write Access
DESCRIPTION
Processor Status Flags Register (8-Bit Register)
This register is set to 80h on all forms of reset.
Unrestricted direct read. Write access to OV, E, C, GPF1, and GPF0 bits only.
PSF.0–E
Equal Flag. This flag reflects the state of the Equal bit of a compare operation. It is 1 when the two
values are equal. It is 0 when the two values are different. Writing a 1 to this bit by software is
effectively set by the Equal flag.
PSF.1–C
Carry Flag. This flag reflects the state of the Carry bit of the active accumulator. Its state may change
after an arithmetic and logical operation. This flag is set to 1 if the last operation resulted in a carry/bor-
row. Otherwise, it is cleared to 0. Writing a 1 to this bit by software is effectively set by the
Carry flag.
PSF.2–OV
PSF.3–GPF0
PSF.4–GPF1
PSF.5
PSF.6–S
Overflow Flag. This flag is set to 1 if there is a carry out of bit 14 but not out of bit 15, or a carry out of
bit 15 bit not out of bit 14 from the last arithmetic operation; otherwise, the OV remains as 0. When add-
ing signed numbers, OV indicates a negative number resulted as the sum of two positive operands, or a
positive sum resulted from two negative operands. For subtraction, OV is set if a borrow is needed into
bit 14 but not into bit 15, or into bit 15 but not into bit 14.
This bit can be read and written by software to allow it to be restored after events such as interrupt
servicing and debug operations.
General-Purpose Flag 0. This is a general-purpose flag for software control.
General-Purpose Flag 1. This is a general-purpose flag for software control.
Reserved. Read returns 0.
Sign Flag. This flag reflects the state of the Sign bit of the active accumulator (the most significant bit of
the active accumulator). Its state may change after an arithmetic and logical operation or after the switch
of the active accumulator. When it is set to 1, it indicates a negative value in the active accumulator from
the last operation. When it is cleared to 0, it indicates a positive value.
PSF.7–Z
IC (05h, 08h)
Initialization
Read/Write Access
IC.0–IGE
Zero Flag. This flag reflects the state of the Zero bit of the active accumulator (bit-wise NOR of the
active accumulator). Its state may change after an arithmetic and logical operation or after the switch
of the active accumulator. When it is set to 1, it indicates a zero value as a result of the last operation.
When it is cleared to 0, it indicates a nonzero value.
Interrupt and Control Register (8-Bit Register)
This register is cleared to 00h on all forms of reset.
Unrestricted read/write.
Interrupt Global Enable. The IGE bit enables the interrupt handler if set to 1. No interrupt to the CPU is
allowed if this bit is cleared to 0.
IC.1–INS
IC[7:2]
IMR (06h, 08h)
Initialization
Read/Write Access
IMR.0–IM0
Interrupt In Service. The INS is set by the interrupt handler automatically when an interrupt is
acknowledged. No further interrupt occurs as long as the INS remains set. The interrupt service routine
can clear the INS to allow interrupt nesting. Otherwise, at the execution of an RETI/POPI instruction, the
INS is cleared automatically by the interrupt handler.
Reserved. Read returns 0.
Interrupt Mask Register (8-Bit Register)
This register is cleared 80h on all forms of reset.
Unrestricted read. All bits have unrestricted write access, unless otherwise stated.
Interrupt Mask 0. This bit is the module level interrupt enable for register module 0. To activate the
interrupt request from module 0, the IGE and IM0 must be set and the INS is not set. Clearing this bit
to 0 disables all interrupt sources in module 0.
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