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MAX1441 Datasheet, PDF (22/41 Pages) Maxim Integrated Products – Automotive, Two-Channel Proximity and Touch Sensor
Automotive, Two-Channel Proximity and
Touch Sensor
Table 10. Special-Function Register Reset Values
REGISTER
PO0
EIF0
EIE0
EIES0
TCON
TFRQ
TCNT
PI0
PD0
BRKPNT
ICDT0
ICDT1
ICDC
ICDF
ICDB
ICDA
ICDD
—
—
—
—
MODULE 0
MSB
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
—
—
—
0000
0000
0000
—
—
—
0000
0000
—
—
—
—
0000
0000
—
—
—
—
0111
0000
0000
0000
0000
0000
0000
ssss
0000
0000
0000
0000
0000
0000
0000
0000
0000
—
—
—
—
LSB
1111
0000
0000
0000
0000
0000
0000
ssss
0000
0000
0000
0000
0000
0000
0000
0000
0000
—
—
—
—
REGISTER
AFEINTST
SCT
CRNG
PD
WU1
WU2
FEL
FEB
CRSLT1L
CRSLT1H
CRSLT2L
CRSLT2H
AT1H
RT1H
AT2H
RT2H
CO1
CO2
DSB
SSB2
AFEIE
MODULE 1
MSB
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0010
0000
0000
0000
0001
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
LSB
0000
0010
0010
0000
0100
0100
1110
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0001
0000
Table 11. Special-Function Register Bit Description
REGISTER
PO0 (00h, 00h)
Initialization
Read/Write Access
DESCRIPTION
Port 0 Output Register (8-Bit Register)
This register is set to 7Fh on all forms of reset.
Unrestricted read/write.
PO0[6:0]
Port 0 Output Register Bits [6:0]. This register stores output data for this port when it is defined as
an output port. Reading from the register returns the contents of the register and does not necessarily
reflect the true state of the port pins. Changing the direction of this port does not change the data con-
tents of the register.
PO0.7
EIF0 (01h, 00h)
Initialization
Read/Write Access
Reserved. Read returns 0.
External Interrupt Flag 0 Register (8-Bit Register)
This register is cleared to 00h on all forms of reset.
Unrestricted read/write.
EIF0[2:0]–IE[2:0]
Interrupt Edge Detect Bits [2:0]. These bits are set when the edge selected by ITx is detected on the
interrupt pin, INTx. Setting any of the bits to 1 generates an interrupt to the CPU if the corresponding
interrupt is enabled. These bits remain set until cleared by software or a reset. It must be cleared by
software before exiting the interrupt source routine or another interrupt is generated as long as the bit
remains set.
EIF0[7:3]
Reserved. Read returns 0.
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