MAX1441 Datasheet, PDF (16/41 Pages) Maxim Integrated Products – Automotive, Two-Channel Proximity and Touch Sensor

Automotive, Two-Channel Proximity and
Touch Sensor
Table 5. Special-Purpose Register Bit Description (continued)
REGISTER
CKCN[3:0]
DESCRIPTION
Reserved. These bits are read only. Read returns 0.
CKCN.4–STOP
Stop Mode Select. Setting this bit to 1 stops program execution and commences low-power CPU
operation. This bit is cleared by a reset or any of the enabled external interrupts. Setting and resetting
the STOP bit does not change the system clock source and its divide ratio.
CKCN[6:5]
Reserved. These bits are read only. Read returns 11b.
CKCN.7–IDLE
IDLE Mode Select. Setting this bit to a 1 stops program execution by halting the instruction pointer and
disabling the internal module selects (similar to a NOP operation). This provides a low-power mode that
does not require a system warm-up on exit.
WDCN (0Fh, 08h)
Initialization
Read/Write Access
Watchdog Timer Control (8-Bit Register)
This register is set to B2h on POR and set to ss00 0ss0b on all other forms of reset.
Unrestricted read. Unrestricted write access, unless stated otherwise.
WDCN.0–RWT
Reset Watchdog Timer. Setting this bit resets the watchdog timer count. This bit must be set before the
watchdog timer expires, or a watchdog timer reset and/or interrupt is generated if enabled. The timeout
period is defined by WD1 and WD0. This bit is always 0 when read.
WDCN.1–EWT
Enable Watchdog Timer Reset. Setting this bit to 1 enables the watchdog timer to reset the device;
clearing this bit to 0 disables the watchdog timer reset. It has no effect on the timer itself and its
ability to generate a watchdog interrupt. This bit is set to 1 following a power-on reset and is unaffected
by all other resets. This bit can only be written once by software. Once written, the value of this bit is
not altered by any subsequent write.
WDCN.2–WTRF
WDCN.3–WDIF
Watchdog Timer Reset Flag. When set, this bit indicates that a watchdog timer reset has occurred. It
is typically interrogated to determine if a reset was caused by the watchdog timer. It is cleared by
power-on reset, but otherwise must be cleared by software before the next reset of any kind to allow
software to work correctly. Setting this bit by software does not generate a watchdog timer reset. If the
EWT bit is cleared, the watchdog timer has no effect on this bit.
Watchdog Interrupt Flag. This bit is set to 1 by a watchdog timeout, which indicates a watchdog timer
event has occurred if EWT and/or EWDI are set. When the WDIF is set, EWT and EWDI determine the
action to take.
Setting this bit from 0 to 1 also activates the reset counter for the watchdog reset timeout, which allows
512 clock cycles for the system to reset the watchdog timer using the RWT bit.
Setting this bit in software generates a watchdog interrupt if enabled and triggers the reset counter.
This bit must be cleared in software before exiting the interrupt service routine, or another interrupt is
generated. The reset counter must be cleared by RWT once started.
EWT
x
0
0
EWDI
x
0
1
WDIF
0
x
1
ACTIONS
No interrupt has occurred.
Watchdog disable, clock is gated off.
Watchdog interrupt has occurred.
1
0
1
No interrupt has been generated. Watchdog reset occurs in 512
clock cycles if RWT is not set or WDIF not cleared.
1
1
1
Watchdog interrupt has occurred. Watchdog reset occurs in 512
clock cycles if RWT is not set or WDIF not cleared.
Note: Software cannot set this flag. Software can only clear this flag. This restriction is specific
to the MAX1441 only and does not apply to other MAXQ products.
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