MAX1441 Datasheet, PDF (18/41 Pages) Maxim Integrated Products – Automotive, Two-Channel Proximity and Touch Sensor

Automotive, Two-Channel Proximity and
Touch Sensor
Table 5. Special-Purpose Register Bit Description (continued)
REGISTER
PFX (00h–07h, 0Bh)
Initialization
Read/Write Access
DESCRIPTION
Prefix Register (16-Bit Register)
This register is cleared to 0000h on all forms of reset.
Unrestricted read/write.
PFX[7:0]
Prefix Register Bits [7:0]. This register provides a means to supply the high-order byte of data to a 16-bit
destination register with 8-bit sources. To transfer 8-bit source data to a 16-bit destination, the high-order
byte must first transfer to the PFX register. This activates the PFX for the next instruction cycle, which
concatenates PFX data with the source operand to form a 16-bit data for the target destination. The PFX
holds data for only one cycle before resetting all its bits to 0. When PFX is used as a source, it basically
transfers a zero value to the destination when PFX has not been activated in the preceding instruction.
PFX[15:8]
IP (00h, 0Ch)
Initialization
Read/Write Access
Prefix Register Bits [15:8]. Reserved. Read returns 0.
Note: Subdecodes (1h–7h) function as extension bits for source/destination indexing.
Instruction Pointer (16-Bit Register)
This register is set to 8000h on all forms of reset.
Unrestricted read/write.
IP[15:0]
Instruction Pointer Bits [15:0]. This register contains the next program address to be fetched by the
fetch unit. The content of IP is automatically incremented by 1 after each fetch. New data written to this
register causes the program flow to branch to the new location. Read access to the IP register does not
affect the program flow.
SP (01h, 0Dh)
Initialization
Read/Write Access
Stack Pointer (16-Bit Register)
This register is cleared to 002Fh on all forms of reset.
Unrestricted read/write.
SP[5:0]
Stack Pointer Bits [5:0]. The SP designates the memory location that is at the top of the stack, which
is the storage location of the last word. The contents of the SP is postdecremented for a POP operation,
and is preincremented for a PUSH operation.
SP[15:6]
IV (02h, 0Dh)
Initialization
Read/Write Access
IV[15:0]
LC0 (06h, 0Dh)
Initialization
Read/Write Access
Reserved. Read returns 0.
Interrupt Vector Register (16-Bit Register)
This register is set to 07FDh on all forms of reset.
Unrestricted read only.
Interrupt Vector Bits [15:0]. This register contains the interrupt vector address. The interrupt handler
forces a hardware call to this vector location when there is an enabled interrupt request pending.
Loop Counter 0 (16-Bit Register)
This register is cleared to 0000h on all forms of reset.
Unrestricted read/write.
LC0[15:0]
Loop Counter 0 Bits [15:0]. This register contains the loop count for a loop operation. The content of
LC0 is automatically decremented by 1 after each loop. This register is normally used as a loop control
for conditional branch to a new location.
LC1 (07h, 0Dh)
Initialization
Read/Write Access
Loop Counter 1 (16-Bit Register)
This register is cleared to 0000h on all forms of reset.
Unrestricted read/write.
LC1[15:0]
Loop Counter 1 Bits [15:0]. This register contains the loop count for a loop operation. The content of
LC1 is automatically decremented by 1 after each loop. This register is normally used as loop control for
conditional branch to a new location.
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