MAX1441 Datasheet, PDF (37/41 Pages) Maxim Integrated Products – Automotive, Two-Channel Proximity and Touch Sensor

Automotive, Two-Channel Proximity and
Touch Sensor
If the reset is caused by watchdog or external sources,
the clock source (5MHz oscillator) remains running, but
no program execution is allowed. When the reset source
is external, the user must remove the reset stimulus.
When power is applied to the device, the power-on delay
removes the stimulus automatically.
Power-On Reset Generation
The device incorporates an internal voltage reference
and comparator to monitor VDD and hold the device
in reset if the supply is out of tolerance. Once VDD has
risen above the VPOR threshold, the device generates a
power-on reset, starts the internal 20MHz, and counts
eight cycles of the derived 5MHz to ensure that Flash
is powered up and the system clock source has had
time to stabilize. The processor then exits the reset state
automatically and starts executing the program at loca-
tion 8000h.
Software can determine that a POR has occurred by
checking the power-on reset flag, POR in the WDCN
register. Software should clear the POR flag after having
read it. The POR is an asynchronous reset source.
Watchdog Timer Reset
The watchdog timer is a free-running timer with a
programmable interval. The watchdog supervises the
processor operation by requiring software to clear the
timer counter before the timeout expires. If the timer is
enabled and software fails to clear it before this interval
expires, the device is placed into a reset state. The reset
state maintains for about 90 system clock cycles. Once
the reset is removed, the processor resumes execution
at address 8000h. Software can determine if a reset is
caused by a watchdog timeout by checking the watch-
dog timer reset flag, WTRF in the WDCN register. This
flag is cleared by software only.
External Reset
If the RESET input is taken to logic 0, the device is forced
into a reset state. An external reset is accomplished by
holding the RESET pin low at least four clock cycles
while the internal 5MHz clock is running. Once the reset
state is invoked, it is maintained as long as RESET is
pulled to logic 0. When the reset state is removed, the
processor exits the reset state within four clock cycles
and begin execution at address 8000h.
If a reset state is applied while the processor is in the
stop mode, the reset causes the processor to exit the
stop mode and forces the program counter to 8000h.
The reset delay is four clock cycles.
The RESET is a bidirectional I/O. If a reset is caused by
a watchdog timer reset or an internal system reset, an
output reset pulse is also generated at the RESET pin.
This reset pulse is asserted as long as a reset source is
asserted and may not be able to drive the reset signal
out if the RESET pin is connected to an RC reset circuitry.
Connecting the RESET pin to a capacitor would not
affect the internal reset condition.
Internal System Reset
An internal system reset can occur in system program-
ming mode when the ROD bit is set to logic 1 while the
SPE bit is 1.
Timer
The device has implemented an 8-bit timer with
an 11-bit prescaler. The operation of the timer is
configurable using the Timer Control register (TCON),
Timer Frequency register (TFRQ), and the Timer Counter
register (TCNT).
The timer is enabled by setting the Timer Enable Bit
(TCON.TMREN) to 1. Once enabled, the timer starts
counting from the initial TCNT value up to the TFRQ limit.
When TCNT = TFRQ, the timer interrupt flag (TMRIF)
is set to 1. This can cause an interrupt to the CPU if
the timer interrupt is enabled (TMRIE = 1). Once the
frequency limit is reached, TCNT is reset to 0 and
continue to count up again.
The timer has two clock sources: system clock and the
32kHz clock. The selection is made using the Timer Clock
Select (TCLK) bit. Due to different clock domains, when
running off the 32kHz clock, reading of the TCNT register
is only valid when the Timer Valid Flag (TVALID) is set to
1. When running the system clock, there is no restriction
on running from TCLK. In addition, a write to TRMEN
when running off the 32kHz clock can be delayed due to
synchronization between the two domains.
To increase the period between subsequent interrupts,
an 11-bit prescaler is provided to prescale the input
clock from 1 to 2048.
If the timer is enabled and running off the 32kHz clock
source prior to the stop mode entry, the timer continues
to run and invoke a stop mode exit if the interrupt is
enabled.
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