MAX1441 Datasheet, PDF (27/41 Pages) Maxim Integrated Products – Automotive, Two-Channel Proximity and Touch Sensor

Automotive, Two-Channel Proximity and
Touch Sensor
Table 11. Special-Function Register Bit Description (continued)
REGISTER
SCT (01h, 01h)
Initialization
Read/Write Access
SCT.0–SCT
DESCRIPTION
Single Conversion Register (8-Bit Register)
This register is cleared to 02h on all forms of reset.
Unrestricted read/write. See the following individual bit definitions for write restriction.
Single Conversion Trigger. Setting this bit to 1 initiates a conversion to an enabled channel (PDx = 0)
when the single conversion mode is enabled. Once set to 1, a write to this bit is ignored. This bit is
automatically cleared to 0 at the end of the conversion.
SCT.1–SCEN
SCT[7:2]
CRNG (02h, 01h)
Initialization
Read/Write Access
CRNG[1:0]–
CRNG1[1:0]
CRNG[3:2]
CRNG[5:4]–
CRNG2[1:0]
CRNG[7:6]
PD (03h, 01h)
Initialization
Read/Write Access
Single Conversion Enable. Setting this bit to 1 enables the single conversion mode. Clearing this bit to
0 disables the single conversion mode.
Reserved. Read returns 0.
Input Range Register (8-Bit Register)
This register is cleared to 22h on all forms of reset.
Unrestricted read/write.
CH1 Capacitance Input Range Bits [1:0]. These bits set the capacitance input range.
CRNG1[1:0]
CAPACITANCE RANGE (pF)
00
5
01
10
10
20
11
20
Reserved. Read returns 0.
CH2 Capacitance Input Range Bits [1:0]. These bits set the capacitance input range.
CRNG2[1:0]
CAPACITANCE RANGE (pF)
00
5
01
10
10
20
11
20
Reserved. Read returns 0.
Power-Down Register (8-Bit Register)
This register is cleared to 0000h on all forms of reset.
Unrestricted read. Write to this register is unrestricted, unless otherwise stated in the following bit
definition.
PD.0–SB
Standby Enable. Setting this bit to 1 enables the standby mode for both channels. Clearing this bit to 0
disables the standby mode. When standby mode is enabled, the conversion occurs at a divided-down
rate as defined by DSB and SSB. Once set, this bit can be cleared by software. This bit is automatically
cleared to 0 if a wake-up event occurs.
PD.1–PD1
PD.2–PD2
PD[7:3]
WU1 (04h, 01h)
Initialization
Read/Write Access
WU1.0–AE1
CH1 Power-Down. Setting this bit to 1 powers down CH1. Clearing this bit to 0 powers up CH1.
CH2 Power-Down. Setting this bit to 1 powers down CH2. Clearing this bit to 0 powers up CH2.
Reserved. Read returns 0.
CH1 Wake-Up Control Register (8-Bit Register)
This register is cleared to 04h on all forms of reset.
Unrestricted read/write.
CH1 Absolute Wake-Up Threshold Enable. Setting this bit to 1 enables the absolute wake-up
threshold detection. Clearing this bit to 0 disables the absolute wake-up threshold detection.
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