MAX1441 Datasheet, PDF (15/41 Pages) Maxim Integrated Products – Automotive, Two-Channel Proximity and Touch Sensor

Automotive, Two-Channel Proximity and
Touch Sensor
Table 5. Special-Purpose Register Bit Description (continued)
REGISTER
DESCRIPTION
IMR.1–IM1
Interrupt Mask 1. This bit is the module level interrupt enable for register module 1. To activate the
interrupt request from module 1, the IGE and IM1 must be set and the INS is not set. Clearing this bit to
0 disables all interrupt sources in module 1.
IMR[6:2]
Reserved. Read returns 0.
IMR.7–IMS
Interrupt Mask 7. This bit is the module level interrupt enable for SPR modules. To activate the interrupt
request from any SPR modules, the IGE and IMS must be set and the INS is not set. Clearing this bit to
0 disables all interrupt sources in all SPR modules.
This bit is read only and defaults to 1 on all forms of reset.
SC (08h, 08h)
Initialization
Read/Write Access
SC.0
System Control Register (8-Bit Register)
This register is set to 82h on POR and set to 1000 00s0b on all other forms of reset.
Unrestricted read. See the following bit definition for write restriction.
Reserved. Read returns 0.
SC.1–PWL
Password Lock. This bit defaults to 1 on a power-on reset. When this bit is 1, it requires a 32-byte
password to be matched with the password in the program space before allowing access to the ROM
loader’s utilities for read/write of program memory and debug functions.
SC.2–ROD
SC[6:3]
SC.7–TAP
IIR (0Bh, 08h)
Initialization
Read/Write Access
IIR.0–II0
IIR.1–II1
IIR[6:2]
IIR.7–IIS
CKCN (0Eh, 08h)
Initialization
Read/Write Access
ROM Operation Done. This bit is used to signify completion of a ROM operation sequence to the con-
trol units. This allows the debug engine to determine the status of a ROM sequence. Setting this bit to
logic 1 causes an internal system reset if the SPE bit is also set. Setting the ROD bit clears the SPE bit
if it is set and the ROD bit is automatically cleared by hardware once the control unit acknowledges the
done indication.
Setting this bit to 1 causes either an internal system reset or the debug engine to execute a com-
mand to clear this bit. Either way, the applicable code is never able to read a 1 from this bit.
Reserved. Read returns 0.
Test Access (JTAG) Port Enable. This bit controls whether the test access port special function pins
are enabled. The TAP defaults to being enabled. Clearing this bit to 0 disables the TAP special function
on the JTAG pins.
Interrupt Identification Register (8-Bit Register)
This register is cleared to 00h on all forms of reset.
Unrestricted direct read. Write access is a no operation.
Interrupt ID 0. When this bit is set to 1, it indicates that there is at least one pending interrupt in module
0. This bit is set only if the interrupt flag and its corresponding enable bit are set. The II0 is cleared by
hardware when the interrupt source is disabled or the flag is cleared by software.
Interrupt ID 1. When this bit is set to 1, it indicates that there is at least one pending interrupt in module
1. This bit is set only if the interrupt flag and its corresponding enable bit are set. The II1 is cleared by
hardware when the interrupt source is disabled or the flag is cleared by software.
Reserved. Read returns 0.
Interrupt ID System. When this bit is set to 1, it indicates that there is at least one pending interrupt in
SPR modules. This bit is set only if the interrupt flag and its corresponding enable bit is set. The IIS is
cleared by hardware when the interrupt source is disabled or the flag is cleared by software.
System Clock Control Register (8-Bit Register)
This register is set to 060h on all forms of resets.
Unrestricted read. See the following bit description for write restriction.
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