MAX1441 Datasheet, PDF (30/41 Pages) Maxim Integrated Products – Automotive, Two-Channel Proximity and Touch Sensor

Automotive, Two-Channel Proximity and
Touch Sensor
Table 11. Special-Function Register Bit Description (continued)
REGISTER
CO1 (10h, 01h)
Initialization
Read/Write Access
CO1[5:0]
CO1[7:6]
CO2 (11h, 01h)
Initialization
Read/Write Access
CO2[5:0]
CO2[7:6]
DSB (12h, 01h)
Initialization
Read/Write Access
DSB[4:0]
DSB[7:5]
SSB2 (13h, 01h)
Initialization
Read/Write Access
DESCRIPTION
Channel 1 Capacitance Offset Register (8-Bit Register)
This register is cleared to 00h on all forms of reset.
Unrestricted read/write.
Channel 1 Capacitance Offset Bits [5:0]. These bits select the amount of capacitance compensation
to be applied. Capacitance can be adjusted in a 1pF increment up to 63pF.
Reserved. Read returns 0.
Channel 2 Capacitance Offset Register (8-Bit Register)
This register is cleared to 00h on all forms of reset.
Unrestricted read/write.
Channel 2 Capacitance Offset Bits [5:0]. These bits select the amount of capacitance compensation
to be applied. Capacitance can be adjusted in a 1pF increment up to 63pF.
Reserved. Read returns 0.
Standby State Conversion Rate Divider Register (8-Bit Register)
This register is cleared to 01h on all forms of reset.
Unrestricted read/write.
Standby State Conversion Rate Divider Bits [4:0]. These bits set the conversion rate divider for both
channels 1 and 2 in the standby state. The conversion rate is reduced by DSB[4:0].
Reserved. Read returns 0.
Channel 2 Standby State Conversion Rate Subdivider Register (8-Bit Register)
This register is cleared to 01h on all forms of reset.
Unrestricted read/write.
SSB2[4:0]
Channel 2 Standby State Conversion Rate Divider Bits [4:0]. These bits set the additional channel 2
conversion rate divider that is applied, in addition to the DSB divide ratio in the standby state. The con-
version rate for channel 2 is divided by DSB[4:0] x SSB2[4:0].
SSB2[7:5]
AFEIE (14h, 01h)
Initialization
Read/Write Access
AFEIE.0–EDR1
Reserved. Read returns 0.
AFE Interrupt Enable Register (8-Bit Register)
This register is cleared to 00h on all forms of reset.
Unrestricted read/write.
CH1 Data Ready Interrupt Enable. Setting this bit to 1 generates an interrupt to the CPU when the IDR1
bit is set to 1. Clearing this bit to 0 disables an interrupt from generating.
AFEIE.1–EDR2
CH2 Data Ready Interrupt Enable. Setting this bit to 1 generates an interrupt to the CPU when the IDR2
bit is set to 1. Clearing this bit to 0 disables an interrupt from generating.
AFEIE.2–EIWUP1
CH1 Wake-Up Event Interrupt Enable. Setting this bit to 1 generates an interrupt to the CPU when
EIWUP1 = 1. Clearing this bit to 0 disables an interrupt from generating.
AFEIE.3–EIWUP2
AFEIE[7:4]
CH2 Wake-Up Event Interrupt Enable. Setting this bit to 1 generates an interrupt to the CPU when
EIWUP2 = 1. Clearing this bit to 0 disables an interrupt from generating.
Reserved. Read returns 0.
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