X9520_07 Datasheet, PDF (8/29 Pages) Intersil Corporation – Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors

X9520
I7 I6 I5 I4 I3 I2 I1 I0
WT 0 0 0 0 0 P1 P0
WRITE TYPE
DCP SELECT
WT^†
DESCRIPTION
0 Select a Volatile Write operation to be performed on the
DCP pointed to by bits P1 and P0
1 Select a Nonvolatile Write operation to be performed on
the DCP pointed to by bits P1 and P0
†_{This bit has no effect when a Read operation is being performed.}
FIGURE 8. INSTRUCTION BYTE FORMAT
The Instruction Byte (Figure 8) is valid only when the Device
Type Identifier and the Internal Device Address bits of the
Slave Address are set to 1010111. In this case, the two
Least Significant Bit’s (I1 - I0) of the Instruction Byte are
used to select the particular DCP (0 - 2). In the case of a
Write to any of the DCPs (i.e. the LSB of the Slave Address
is 0), the Most Significant Bit of the Instruction Byte (I7),
determines the Write Type (WT) performed.
If WT is “1”, then a Nonvolatile Write to the DCP occurs. In
this case, the “wiper position” of the DCP is changed by
simultaneously writing new data to the associated WCR and
NVM. Therefore, the new “wiper position” setting is recalled
into the WCR after V1/VCC of the X9520 has been powered
down then powered back up
If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing new
data to the associated WCR only. The contents of the
associated NVM register remains unchanged. Therefore,
when V1/VCC to the device is powered down then back up,
the “wiper position” reverts to that last written to the DCP
using a nonvolatile write operation.
DCP Write Operation
A write to DCPx (x = 0,1,2) can be performed using the three
byte command sequence shown in Figure 9.
In order to perform a write operation on a particular DCP, the
Write Enable Latch (WEL) bit of the CONSTAT Register
must first be set (See “BL1, BL0: Block Lock protection bits -
(Nonvolatile)” on page 13.)
The Slave Address Byte 10101110 specifies that a Write to a
DCP is to be conducted. An ACKNOWLEDGE is returned by
the X9520 after the Slave Address, if it has been received
correctly.
Next, an Instruction Byte is issued on SDA. Bits P1 and P0
of the Instruction Byte determine which WCR is to be written,
while the WT bit determines if the Write is to be volatile or
nonvolatile. If the Instruction Byte format is valid, another
ACKNOWLEDGE is then returned by the X9520.
Following the Instruction Byte, a Data Byte is issued to the
X9520 over SDA. The Data Byte contents is latched into the
WCR of the DCP on the first rising edge of the clock signal,
after the LSB of the Data Byte (D0) has been issued on SDA
(See Figure 34).
The Data Byte determines the “wiper position” (which FET
switch of the DCP resistive array is switched ON) of the
DCP. The maximum value for the Data Byte depends upon
which DCP is being addressed (see Table below).
P1 - P0
00
01
10
11
DCPX
x=0
x=1
x=2
# TAPS
MAX DATA BYTE
64
3Fh
100
Refer to Appendix 1
256
FFh
Reserved
Using a Data Byte larger than the values specified above
results in the “wiper terminal” being set to the highest tap
position. The “wiper position” does NOT roll-over to the
lowest tap position.
For DCP0 (64 Tap) and DCP2 (256 Tap), the Data Byte
maps one to one to the “wiper position” of the DCP “wiper
S ^{1 0 1 0 1 1 1 0} A WT 0 0 0 0 0 P1 P0 A ^{D7 D6 D5 D4 D3 D2 D1 D0} A S
T
C
C
CT
A
K
K
KO
R
T
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
DATA BYTE
P
FIGURE 9. DCP WRITE COMMAND SEQUENCE
8
FN8206.2
August 20, 2007