X9520_07 Datasheet, PDF (20/29 Pages) Intersil Corporation – Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors

X9520
AC Characteristics (See Figure 27, Figure 28, Figure 29)
SYMBOL
f_SCL
t_IN (Note 5)
t_AA (Note 5)
t_BUF
t_LOW
t_HIGH
t_SU:STA
t_HD:STA
t_SU:DAT
t_HD:DAT
t_SU:STO
t_DH (Note 5)
t_R (Note 5)
t_F (Note 5)
t_SU:WP
t_HD:WP
Cb (Note 5)
PARAMETER
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
WP Hold Time
Capacitive load for each bus line
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
Nonvolatile Write Cycle Timing
SYMBOL
PARAMETER
t_WC (Note 4)
Nonvolatile Write Cycle Time
400kHz
MIN
0
50
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 +.1Cb (Note 2)
20 +.1Cb (Note 2)
0.6
0
MAX
400
0.9
300
300
400
UNITS
kHz
ns
μs
μs
μs
μs
μs
μs
ns
μs
μs
ns
ns
ns
μs
μs
pF
0.1V_CC to 0.9V_CC
10ns
0.5V_CC
See Figure 25
MIN TYP (Note 1) MAX
5
10
UNITS
ms
Capacitance (T_A = +25°C, f = 1.0MHz, V_CC = 5V)
SYMBOL
PARAMETER
MAX
UNITS
TEST CONDITIONS
C_OUT (Note 5) Output Capacitance (SDA, V1RO, V2RO, V3RO)
8
pF
V_OUT = 0V
C_IN (Note 5) Input Capacitance (SCL, WP, MR)
6
pF
V_IN = 0V
NOTES:
1. Typical values are for T_A = 25°C and V_CC = 5.0V.
2. Cb = total capacitance of one bus line in pF.
3. Over recommended operating conditions, unless otherwise specified.
4. t_WC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
5. This parameter is not 100% tested.
20
FN8206.2
August 20, 2007