X9520_07 Datasheet, PDF (15/29 Pages) Intersil Corporation – Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors

X9520
Signals from the
Master
SDA Bus
Signals from the
Slave
WRITE Operation
READ Operation
S
S
t
t
S
a
Slave
r
Address
t
Address
Byte
a
r
Slave
t ^Address
t
o
p
10 1 0 0 1 0 0
A
C
K
CS7 … CS0
10 1 0 0 1 01
A
A
C
C
K
K
Data
“Dummy” Write
FIGURE 19. CONSTAT REGISTER READ COMMAND SEQUENCE
Data Protection
There are a number of levels of data protection features
designed into the X9520. Any write to the device first
requires setting of the WEL bit in the CONSTAT register. A
write to the CONSTAT register itself, further requires the
setting of the RWEL bit. Block Lock protection of the device
enables the user to inhibit writes to certain regions of the
EEPROM memory, as well as to all the DCPs. One further
level of data protection in the X9520, is incorporated in the
form of the Write Protection pin.
WP: Write Protection Pin
When the Write Protection (WP) pin is active (HIGH), it
disables nonvolatile write operations to the X9520.
The table below (X9520 Write Permission Status)
summarizes the effect of the WP pin (and Block Lock), on
the write permission status of the device.
Additional Data Protection Features
In addition to the preceding features, the X9520 also
incorporates the following data protection functionality:
• The proper clock count and data bit sequence is required
prior to the STOP bit in order to start a nonvolatile write
cycle.
Voltage Monitoring Functions
V1/VCC Monitoring
The X9520 monitors the supply voltage and drives the V1RO
output HIGH (using an external “pull up” resistor) if V1/VCC
is lower than V_TRIP1 threshold. The V1RO output will remain
HIGH until V1/VCC exceeds V_TRIP1 for a minimum time of
t_PURST. After this time, the V1RO pin is driven to a LOW
state. See Figure 30.
For the Power-on/Low Voltage Reset function of the X9520,
the V1RO output may be driven HIGH down to a V1/VCC of
1V (V_RVALID). See Figure 30. Another feature of the X9520,
15
V1/VCC
MR
0 Volts
0 Volts
V_TRIP1
V1RO
0 Volts
t_PURST
FIGURE 20. MANUAL RESET RESPONSE
is that the value of t_PURST may be selected in software via
the CONSTAT register (See “POR1, POR0: Power-on Reset
bits – (Nonvolatile)” on page 13.).
It is recommended to stop communication to the device
while V1R0 is HIGH. Also, setting the Manual Reset (MR)
pin HIGH overrides the Power-on/Low Voltage circuitry and
forces the V1RO output pin HIGH (See "MR: Manual
Reset").
MR: Manual Reset
The V1RO output can be forced HIGH externally using the
Manual Reset (MR) input. MR is a de-bounced, TTL
compatible input, and so it may be operated by connecting a
push-button directly from V1/VCC to the MR pin.
V1RO remains HIGH for time t_PURST after MR has returned
to its LOW state (See Figure 20). An external “pull down”
resistor is required to hold this pin (normally) LOW.
FN8206.2
August 20, 2007