X9520_07 Datasheet, PDF (17/29 Pages) Intersil Corporation – Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors

X9520
initiates the programming sequence. Pin WP must then be
brought LOW to complete the operation (See Figure 23).The
user does not have to set the WEL bit in the CONSTAT
register before performing this write sequence.
After being reset, the value of V_TRIPx becomes a nominal
value of 1.7V.
V_TRIPx Accuracy (x = 1,2,3).
The accuracy with which the V_TRIPx thresholds are set, can
be controlled using the iterative process shown in Figure 24.
If the desired threshold is less that the present threshold
voltage, then it must first be “reset” (See "Resetting the
VTRIPx Voltage (x = 1,2,3).").
The desired threshold voltage is then applied to the appropriate
input pin (V1/VCC, V2 or V3) and the procedure described in
Section “Setting a Higher V_TRIPx Voltage“ must be followed.
Once the desired V_TRIPx threshold has been set, the error
between the desired and (new) actual set threshold can be
determined. This is achieved by applying V1/VCC to the
device, and then applying a test voltage higher than the desired
threshold voltage, to the input pin of the voltage monitor circuit
whose V_TRIPx was programmed. For example, if V_TRIP2 was
set to a desired level of 3.0 V, then a test voltage of 3.4 V may
be applied to the voltage monitor input pin V2. In the case of
setting of V_TRIP1 then only V1/VCC need be applied. In all
cases, care should be taken not to exceed the maximum input
voltage limits.
After applying the test voltage to the voltage monitor input
pin, the test voltage can be decreased (either in discrete
steps, or continuously) until the output of the voltage monitor
circuit changes state. At this point, the error between the
actual/measured, and desired threshold levels is calculated.
For example, the desired threshold for V_TRIP2 is set to 3.0 V,
and a test voltage of 3.4 V was applied to the input pin V2 (after
V1/VCC
V2, V3
WP
SCL
SDA
V_TRIPx
V_P
0 1 23 4 56 7
0 1 23 4 56 7
0 1 23 4 56 7
00h
†
A0h
S
T
A
R
01h^†
09h^†
0Dh^†
sets
sets
sets
V_TRIP1
V_TRIP2
V_TRIP3
Data Byte ^†
† _{All others Reserved.}
T
FIGURE 22. SETTING V_TRIPX TO A HIGHER LEVEL (X = 1,2,3).
WP
SCL
SDA
V_P
0 1 23 4 56 7
0 1 23 4 56 7
0 1 23 4 56 7
00h ^†
A0h^†
03h^† Resets VTRIP1
Data Byte
S
T
0Bh^† Resets VTRIP2
A
R
0Fh^† Resets VTRIP3
T
† _{All others Reserved.}
FIGURE 23. RESETTING THE V_TRIPx LEVEL
17
FN8206.2
August 20, 2007