X9520_07 Datasheet, PDF (6/29 Pages) Intersil Corporation – Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors

X9520
SA7 SA6 SA5 SA4 SA3 SA2 SA1 _SA0
101 0
R/W
DEVICE TYPE
IDENTIFIER
INTERNAL
DEVICE
ADDRESS
READ/
WRITE
INTERNAL ADDRESS INTERNALLY ADDRESSED
(SA3 - SA1)
DEVICE
000
EEPROM Array
010
CONSTAT Register
111
DCP
BIT SA0
0
1
OPERATION
WRITE
READ
FIGURE 4. SLAVE ADDRESS FORMAT
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either the
EEPROM array, the Non Volatile Memory of a DCP (NVM),
or the CONSTAT Register) has been correctly issued
(including the final STOP condition), the X9520 initiates an
internal high voltage write cycle. This cycle typically requires
5 ms. During this time, no further Read or Write commands
can be issued to the device. Write Acknowledge Polling is
used to determine when this high voltage write cycle has
been completed.
To perform acknowledge polling, the master issues a START
condition followed by a Slave Address Byte. The Slave
Address issued must contain a valid Internal Device
Address. The LSB of the Slave Address (R/W) can be set to
either 1 or 0 in this case. If the device is still busy with the
high voltage cycle then no ACKNOWLEDGE will be
returned. If the device has completed the write operation, an
ACKNOWLEDGE will be returned and the host can then
proceed with a read or write operation (Refer to Figure 5.).
Digitally Controlled Potentiometers
DCP Functionality
The X9520 includes three independent resistor arrays.
These arrays respectively contain 63, 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R_Hx and R_Lx
inputs - where x = 0,1,2).
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
Issue STOP
ACK
returned?
YES
High Voltage Cycle
complete. Continue
command sequence?
NO
NO
Issue STOP
YES
Continue normal
Read or Write
command sequence
PROCEED
FIGURE 5. ACKNOWLEDGE POLLING SEQUENCE
N
R_Hx
WIPER
COUNTER
REGISTER
(WCR)
NON
VOLATILE
MEMORY
(NVM)
DECODER
2
1
0
“WIPER” _RESISTOR
FET
ARRAY
SWITCHES
FIGURE 6. DCP INTERNAL STRUCTURE
R_Lx
R_Wx
6
FN8206.2
August 20, 2007