X9520_07 Datasheet, PDF (2/29 Pages) Intersil Corporation – Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors

Block Diagram
WP
SDA
SCL
MR
V3
V2
V1/VCC
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
THRESHOLD
RESET LOGIC
X9520
8
PROTECT LOGIC
CONSTAT
REGISTER
4
2kbit
EEPROM
ARRAY
2
-
VTRIP₃
+
-
VTRIP ₂
+
+
VTRIP₁
-
WIPER
COUNTER
REGISTER
6 - BIT
NONVOLATILE
MEMORY
WIPER
COUNTER
REGISTER
7 - BIT
NONVOLATILE
MEMOR Y
WIPER
COUNTER
REGISTER
8 - BIT
NONVOLATILE
MEMOR Y
POWER-ON /
LOW VOLTAGE
RESET
GENERATION
R_H0
R_W0
R_L0
R_H1
R_W1
R_L1
R_H2
R_W2
R_L2
V3RO
V2RO
V1RO
Detailed Device Description
The X9520 combines three Intersil Digitally Controlled
Potentiometer (DCP) devices, V1/VCC power-on reset
control, V1/VCC low voltage reset control, two
supplementary voltage monitors, and integrated EEPROM
with Block Lock™ protection, in one package. These
functions are suited to the control, support, and monitoring of
various system parameters in Fiber Channel/Gigabit
Ethernet fiber optic modules, such as in Gigabit Interface
Converter (GBIC) applications. The combination of the
X9520 fucntionality lowers system cost, increases reliability,
and reduces board space requirements using Intersil’s
unique XBGA™ packaging.
Two high resolution DCPs allow for the “set-and-forget”
adjustment of Laser Driver IC parameters such as Laser
Diode Bias and Modulation Currents. One lower resolution
DCP may be used for setting sundry system parameters
such as maximum laser output power (for eye safety
requirements).
Applying voltage to V_CC activates the Power-on Reset circuit
which allows the V1RO output to go HIGH, until the supply
the supply voltage stabilizes for a period of time (selectable
via software). The V1RO output then goes LOW. The Low
Voltage Reset circuitry allows the V1RO output to go HIGH
when V_CC falls below the minimum V_CC trip point. V1RO
remains HIGH until V_CC returns to proper operating level. A
Manual Reset (MR) input allows the user to externally trigger
the V1RO output (HIGH).
Two supplementary Voltage Monitor circuits continuously
compare their inputs to individual trip voltages. If an input
voltage exceeds it’s associated trip level, a hardware output
(V3RO, V2RO) are allowed to go HIGH. If the input voltage
becomes lower than it’s associated trip level, the
corresponding output is driven LOW. A corresponding binary
representation of the two monitor circuit outputs (V2RO and
V3RO) are also stored in latched, volatile (CONSTAT)
register bits. The status of these two monitor outputs can be
read out via the 2-wire serial port.
An application of the V1RO output may be to drive the
“ENABLE” input of a Laser Driver IC, with MR as a
“TX_DISABLE” input. V2RO and V3RO may be used to
monitor “TX_FAULT” and “RX_LOS” conditions respectively.
Intersil’s unique circuits allow for all internal trip voltages to
be individually programmed with high accuracy. This gives
the designer great flexibility in changing system parameters,
either at the time of manufacture, or in the field.
The memory portion of the device is a CMOS serial
EEPROM array with Intersil’s Block Lock™ protection. This
memory may be used to store fiber optic module
manufacturing data, serial numbers, or various other system
parameters. The EEPROM array is internally organized as x
8, and utilizes Intersil’s proprietary Direct Write™ cells,
providing a minimum endurance of 1,000,000 cycles and a
minimum data retention of 100 years.
The device features a 2-Wire interface and software protocol
allowing operation on an I²C™ compatible serial bus.
2
FN8206.2
August 20, 2007