X9520_07 Datasheet, PDF (13/29 Pages) Intersil Corporation – Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors

X9520
CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0
POR1 V2OS V3OS BL1 BL0 RWEL WEL _POR0
NV
NV NV
NV
BIT(S)
DESCRIPTION
WEL
Write Enable Latch bit
RWEL
Register Write Enable Latch bit
V2OS
V2 Output Status flag
V3OS
V3 Output Status flag
BL1 - BL0
Sets the Block Lock partition
POR1 - POR0
Sets the Power-on Reset time
NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
FIGURE 17. CONSTAT REGISTER FORMAT
DCPs, EEPROM array, as well as the CONSTAT register, is
aborted and no ACKNOWLEDGE is issued after a Data
Byte.
The WEL bit is a volatile latch that powers up in the disabled,
LOW (0) state. The WEL bit is enabled/set by writing
00000010 to the CONSTAT register. Once enabled, the WEL
bit remains set to “1” until either it is reset to “0” (by writing
00000000 to the CONSTAT register) or until the X9520
powers down, and then up again.
Writes to the WEL bit do not cause an internal high voltage
write cycle. Therefore, the device is ready for another
operation immediately after a STOP condition is executed in
the CONSTAT Write command sequence (See Figure 18).
RWEL: REGISTER WRITE ENABLE LATCH (VOLATILE)
The RWEL bit controls the (CONSTAT) Register Write
Enable status of the X9520. Therefore, in order to write to
any of the bits of the CONSTAT Register (except WEL), the
RWEL bit must first be set to “1”. The RWEL bit is a volatile
bit that powers up in the disabled, LOW (“0”) state.
It must be noted that the RWEL bit can only be set, once the
WEL bit has first been enabled (See "CONSTAT Register
Write Operation").
The RWEL bit will reset itself to the default “0” state, in one
of three cases:
• After a successful write operation to any bits of the
CONSTAT register has been completed (See Figure 18).
• When the X9520 is powered down.
• When attempting to write to a Block Lock protected region
of the EEPROM memory (See "BL1, BL0: Block Lock
protection bits - (Nonvolatile)").
BL1, BL0: BLOCK LOCK PROTECTION BITS -
(NONVOLATILE)
The Block Lock protection bits (BL1 and BL0) are used to:
• Inhibit a write operation from being performed to certain
addresses of the EEPROM memory array
• Inhibit a DCP write operation (changing the “wiper
position”)
The region of EEPROM memory which is protected/locked is
determined by the combination of the BL1 and BL0 bits
written to the CONSTAT register. It is possible to lock the
regions of EEPROM memory shown in the table below:
PROTECTED ADDRESSES
BL1 BL0
(SIZE)
0
0
None (Default)
0
1
C0h - FFh (64 bytes)
1
0
80h - FFh (128 bytes)
1
1
00h - FFh (256 bytes)
PARTITION OF
ARRAY LOCKED
None (Default)
Upper 1/4
Upper 1/2
All
If the user attempts to perform a write operation on a
protected region of EEPROM memory, the operation is
aborted without changing any data in the array.
When the Block Lock bits of the CONSTAT register are set to
something other than BL1 = 0 and BL0 = 0, then the “wiper
position” of the DCPs cannot be changed - i.e. DCP write
operations cannot be conducted:
BL1 BL0
0
0
0
1
1
0
1
1
DCP WRITE OPERATION PERMISSABLE
YES (Default)
NO
NO
NO
The factory default setting for these bits are BL1 = 0, BL0 = 0.
IMPORTANT NOTE: If the Write Protect (WP) pin of the
X9520 is active (HIGH), then all nonvolatile write operations
to both the EEPROM memory and DCPs are inhibited,
irrespective of the Block Lock bit settings (See "WP: Write
Protection Pin").
POR1, POR0: POWER-ON RESET BITS – (NONVOLATILE)
Applying voltage to V_CC activates the Power-on Reset circuit
which holds V1RO output HIGH, until the supply voltage
stabilizes above the V_TRIP1 threshold for a period of time,
t_PURST (See Figure 30).
The Power-on Reset bits, POR1 and POR0 of the CONSTAT
register determine the t_PURST delay time of the Power-on
Reset circuitry (See "Voltage Monitoring Functions"). These
bits of the CONSTAT register are nonvolatile, and therefore
power-up to the last written state.
13
FN8206.2
August 20, 2007