X9520_07 Datasheet, PDF (5/29 Pages) Intersil Corporation – Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors

SC_SL_Cfr_Lom
M_fra_os_mter
Master
Data Output from
Transmitter
X9520
1
8
9
Data Output from
Receiver
START
ACKNOWLEDGE
FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER
SERIAL ACKNOWLEDGE
An ACKNOWLEDGE (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to ACKNOWLEDGE that it received the eight
bits of data. Refer to Figure 3.
The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device
Identifier bits are contained in the Slave Address Byte. If a
write operation is selected, the device will respond with an
ACKNOWLEDGE after the receipt of each subsequent eight
bit word.
In the read mode, the device will transmit eight bits of data,
release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected and
no STOP condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an ACKNOWLEDGE is not
detected. The master must then issue a STOP condition to
place the device into a known state.
Device Internal Addressing
Addressing Protocol Overview
The user addressable internal components of the X9520 can
be split up into three main parts:
• Three Digitally Controlled Potentiometers (DCPs)
• EEPROM array
• Control and Status (CONSTAT) Register
Depending upon the operation to be performed on each of
these individual parts, a 1, 2 or 3 Byte protocol is used. All
operations however must begin with the Slave Address Byte
being issued on the SDA pin. The Slave address selects the
part of the X9520 to be addressed, and specifies if a Read or
Write operation is to be performed.
It should be noted that in order to perform a write operation
to either a DCP or the EEPROM array, the Write Enable
Latch (WEL) bit must first be set (See “BL1, BL0: Block Lock
protection bits - (Nonvolatile)” on page 13.)
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4). This byte consists of
three parts:
• The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4). The
Device Type Identifier must always be set to 1010 in order
to select the X9520.
• The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 000 internally selects
the EEPROM array, while setting these bits to 111 selects
the DCP structures in the X9520. The CONSTAT Register
may be selected using the Internal Device Address 010.
• The Least Significant Bit of the Slave Address (SA0) Byte
is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined in
the bits SA3 - SA1). When the R/W bit is “1”, then a READ
operation is selected. A “0” selects a WRITE operation
(Refer to Figure 4.)
5
FN8206.2
August 20, 2007