X9520_07 Datasheet, PDF (12/29 Pages) Intersil Corporation – Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors

X9520
WRITE Operation
READ Operation
S
S
Signals from the
Master
t
a
Slave
r
Address
t
Address
Byte
t
a
r
Slave
Address
S
t
o
p
t
SDA Bus
Signals from the
Slave
1 0 1 0 0 0 0₀
A
C
K
1 0 1 0 0 0 01
A
A
C
C
K
K
Data
“Dummy” Write
FIGURE 15. RANDOM EEPROM ADDRESS READ SEQUENCE
the read operation by not responding with an
ACKNOWLEDGE and instead issuing a STOP condition
(Refer to Figure 15.).
A similar operation called “Set Current Address” also exists.
This operation is performed if a STOP is issued instead of
the second START shown in Figure 15. In this case, the
device sets the address pointer to that of the Address Byte,
and then goes into standby mode after the STOP bit. All bus
activity will be ignored until another START is detected.
Sequential EEPROM Read
Sequential reads can be initiated as either a current address
read or random address read. The first Data Byte is
transmitted as with the other modes; however, the master
now responds with an ACKNOWLEDGE, indicating it
requires additional data. The X9520 continues to output a
Data Byte for each ACKNOWLEDGE received. The master
terminates the read operation by not responding with an
ACKNOWLEDGE and instead issuing a STOP condition.
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address counter
for read operations increments through the entire memory
contents to be serially read during one operation. At the end of
the address space the counter “rolls over” to address 00h and
the device continues to output data for each
ACKNOWLEDGE received (Refer to Figure 16.).
Control and Status Register
The Control and Status (CONSTAT) Register provides the
user with a mechanism for changing and reading the status
of various parameters of the X9520 (See Figure 17).
The CONSTAT register is a combination of both volatile and
nonvolatile bits. The nonvolatile bits of the CONSTAT
register retain their stored values even when V1/VCC is
powered down, then powered back up. The volatile bits
however, will always power-up to a known logic state “0”
(irrespective of their value at power-down).
A detailed description of the function of each of the
CONSTAT register bits follows:
WEL: WRITE ENABLE LATCH (VOLATILE)
The WEL bit controls the Write Enable status of the entire
X9520 device. This bit must first be enabled before ANY
write operation (to DCPs, EEPROM memory array, or the
CONSTAT register). If the WEL bit is not first enabled, then
ANY proceeding (volatile or nonvolatile) write operation to
Signals from the
Master
SDA Bus
Signals from the
Slave
S
Slave
A
A
A
t
Address
C
C
C
o
K
K
K
p
0001
A
C
K
Data
(1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
FIGURE 16. SEQUENTIAL EEPROM READ SEQUENCE
12
FN8206.2
August 20, 2007