X9520_07 Datasheet, PDF (22/29 Pages) Intersil Corporation – Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors

X9520
V1RO, V2RO, V3RO Output Timing. (See Figure 30, Figure 31, Figure 32)
SYMBOL
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNITS
t_PURST (Note 5)
Power On Reset delay time
POR1 = 0, POR0 = 0
POR1 = 0, POR0 = 1
25
50
75
ms
50
100
150
ms
POR1 = 1, POR0 = 0
100
200
300
ms
POR1 = 1, POR0 = 1
150
300
450
ms
t_MRD (Figure 31)
(Note 2) (Note 5)
MR to V1RO propagation delay
See (Note 1) (Note 2) (Note 4)
5
μs
t_MRDPW (Note 5)
t_RPDx (Note 5)
MR pulse width
V1/VCC, V2, V3 to V1RO, V2RO, V3RO
propagation delay (respectively)
500
ns
20
μs
t_Fx (Note 5)
t_Rx (Note 5)
V_RVALID (Note 5)
V1/VCC, V2, V3 Fall Time
V1/VCC, V2, V3 Rise Time
V1/VCC for V1RO, V2RO, V3RO Valid
(Note 3).
20
mV/μs
20
mV/μs
1
V
NOTES:
1. See Figure 31 for timing diagram.
2. See Figure 25 for equivalent load.
3. This parameter describes the lowest possible V1/VCC level for which the outputs V1RO, V2RO, and V3RO will be correct with respect to their
inputs (V1/VCC, V2, V3).
4. From MR rising edge crossing V_IH, to V1RO rising edge crossing V_OH.
5. The above parameters are not 100% tested.
V1/VCC = 5V
2300Ω
SDA
V2RO
V3RO
V1RO
100pF
FIGURE 25. EQUIVALENT AC CIRCUIT
Timing Diagrams
R_Hx
R_TOTAL
C_H
R_W
R_Lx
C_L
10pF
10pF
C_W
25pF
(x = 0,1,2)
R_Wx
FIGURE 26. DCP SPICE MACROMODEL
SCL
t_SU:STA
SDA IN
SDA OUT
t_F
t_HIGH
t_SU:DAT
t_HD:STA
t_LOW
t_HD:DAT
t_R
t_AA t_DH
FIGURE 27. BUS TIMING
t_SU:STO
t_BUF
22
FN8206.2
August 20, 2007