X9520_07 Datasheet, PDF (23/29 Pages) Intersil Corporation – Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors

SCL
SDA IN
WP
START
X9520
Clk 1
Clk 9
t_SU:WP
t_HD:WP
FIGURE 28. WP PIN TIMING
SCL
SDA
8th BIT OF LAST BYTE
ACK
t_WC
STOP
CONDITION
START
CONDITION
FIGURE 29. WRITE CYCLE TIMING
V1/VCC
0V
V1RO
0V
MR
0V
t_R
t_PURST
t_RPD
t_PURST
tF
V_TRIP1
t_RPD
FIGURE 30. POWER-UP AND POWER-DOWN TIMING
23
FN8206.2
August 20, 2007