X9520_07 Datasheet, PDF (11/29 Pages) Intersil Corporation – Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors

X9520
7 BYTES
5 byte5sBYTES
ADDRESS = 6₁₀
ADDRESS = 15₁₀
ADDRESS = 11₁₀
ADDRESS POINTER
ENDS HERE
ADDRESS = 7₁₀
FIGURE 13. EXAMPLE: WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 11.
S
SIGNALS FROM
THE MASTER
T
A
R
SLAVE
T
ADDRESS
S
T
O
P
SDA BUS
SIGNALS FROM
THE SLAVE
1 0 1 0 0 0 0₁
A
C
K
DATA
FIGURE 14. CURRENT EEPROM ADDRESS READ SEQUENCE
EEPROM Array Read Operations
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the Slave
Address Byte is set to one. There are three basic read
operations: Current EEPROM Address Read, Random
EEPROM Read, and Sequential EEPROM Read.
Current EEPROM Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n+1. On
power-up, the address of the address counter is undefined,
requiring a read or write operation for initialization.
Upon receipt of the Slave Address Byte with the R/W bit set
to one, the device issues an ACKNOWLEDGE and then
transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond with
an ACKNOWLEDGE during the ninth clock and then issues
a STOP condition (See Figure 14 for the address,
ACKNOWLEDGE, and data transfer sequence).
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a STOP condition during the
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a STOP condition.
Another important point to note regarding the “Current
EEPROM Address Read” , is that this operation is not
available if the last executed operation was an access to a
DCP or the CONSTAT Register (i.e.: an operation using the
Device Type Identifier 1010111 or 1010010). Immediately
after an operation to a DCP or CONSTAT Register is
performed, only a “Random EEPROM Read” is available.
Immediately following a “Random EEPROM Read” , a
“Current EEPROM Address Read” or “Sequential EEPROM
Read” is once again available (assuming that no access to a
DCP or CONSTAT Register occur in the interim).
Random EEPROM Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master issues
the START condition and the Slave Address Byte, receives
an ACKNOWLEDGE, then issues an Address Byte. This
“dummy” Write operation sets the address pointer to the
address from which to begin the random EEPROM read
operation.
After the X9520 acknowledges the receipt of the Address
Byte, the master immediately issues another START
condition and the Slave Address Byte with the R/W bit set to
one. This is followed by an ACKNOWLEDGE from the
X9520 and then by the eight bit word. The master terminates
11
FN8206.2
August 20, 2007