HMP8116 Datasheet, PDF (8/43 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8116
made 254.
While BLANK is asserted, Y is forced to have a value of 16,
with Cb and Cr forced to have a value of 128, unless VBI
data is present.
fications specify a gamma of 2.8, a gamma of 2.2 is normally
used. The HMP8116 allows the selection of the gamma to
be either 2.2 or 2.8, independent of the video standard.
for gamma = 2.2:
RGB OUTPUT FORMAT PROCESSING
The 4:2:2 YCbCr data is converted to 4:4:4 YCbCr data and
then converted to either 15-bit or 16-bit gamma-corrected
RGB (R′G′B′) data. While BLANK is asserted, RGB data is
forced to a value of 0.
15-Bit R′G′B′
The following YCbCr to R′G′B′ equations are used to main-
tain the proper black and white levels:
R′ = 0.142(Y - 16) + 0.194(Cr - 128)
G′ = 0.142(Y - 16) - 0.099(Cr - 128) - 0.048(Cb - 128)
B′ = 0.142(Y - 16) + 0.245(Cb - 128)
The resulting 15-bit R′G′B′ data has a range of 0 to 31. Val-
ues less than 0 are made 0 and values greater than 31 are
made 31.
The 15-bit R′G′B′ data may be converted to 15-bit linear
RGB, using the following equations. Although the PAL speci-
fications specify a gamma of 2.8, a gamma of 2.2 is normally
used. The HMP8116 allows the selection of the gamma to
be either 2.2 or 2.8, independent of the video standard.
for gamma = 2.2:
for R′G′B′ < 0.0812*31
R = (31)((R′/31)/4.5)
G = (31)((G′/31)/4.5)
B = (31)((B′/31)/4.5)
for R′G′B′ >= 0.0812*31
R = (31)(((R′/31) + 0.099)/1.099)^2.2
G = (31)(((G′/31) + 0.099)/1.099)^2.2
B = (31)(((B′/31) + 0.099)/1.099)^2.2
for gamma = 2.8:
R = (31)(R′/31)^2.8
G = (31)(G′/31)^2.8
B = (31)(B′/31)^2.8
16-Bit R′G′B′
The following YCbCr to R′G′B′ equations are used to main-
tain the proper black and white levels:
R′ = 0.142(Y - 16) + 0.194(Cr - 128)
G′ = 0.288(Y - 16) - 0.201(Cr - 128) - 0.097(Cb - 128)
B′ = 0.142(Y - 16) + 0.245(Cb - 128)
The resulting 16-bit R′G′B′ data has a range of 0 to 31 for R′
and B′, and a range of 0 to 63 for G′. Values less than 0 are
made 0; R′ and B′ values greater than 31 are made 31, G′
values greater than 63 are made 63.
The 16-bit R′G′B′ data may be converted to 16-bit linear
RGB, using the following equations. Although the PAL speci-
for R′B′ < 0.0812*31, G′ < 0.0812*63
R = (31)((R′/31)/4.5)
G = (63)((G′/63)/4.5)
B = (31)((B′/31)/4.5)
for R′B′ >= 0.0812*31, G′ >= 0.0812*63
R = (31)(((R′/31) + 0.099)/1.099)^2.2
G = (63)(((G′/63) + 0.099)/1.099)^2.2
B = (31)(((B′/31) + 0.099)/1.099)^2.2
for gamma = 2.8:
R = (31)(R′/31)^2.8
G = (63)(G′/63)^2.8
B = (31)(B′/31)^2.8
BUILT-IN VIDEO GENERATION
When the blue screen, black screen or color bar output is
selected, a full-screen of blue, black or 75% colorbar output
is generated using the currently selected output format. The
type of screen to be generated is determined by bits 2 and 1
of the OUTPUT FORMAT register 02_H. When built-in video
generation is not desired, the bits need to be set for normal
operation to pass decoded video.
If a video source is input, it will be used to provide the video
timing. If an input video source is not detected, internally-
generated video timing will be used.
Pixel Port Timing
The the timing and format of the output data and control sig-
nals is presented in the following sections.
HSYNC AND VSYNC TIMING
The HSYNC and VSYNC output timing is VMI v1.4 compati-
ble. Figures 4-7 illustrate the video timing. The leading edge of
HSYNC is synchronous to the video input signal and has a
fixed latency due to internal pipeline processing. The pulse
width of the HSYNC is defined by the END HSYNC register
36_H, where the trailing edge of HSYNC has a programmable
delay of 0-510 CLK2 cycles from the leading edge.
The leading edge of VSYNC is asserted approximately half
way through the first serration pulse of each field. For an odd
field, the trailing edge of VSYNC is 5±1 CLK2 cycles after the
trailing edge of the HSYNC that follows the last equalization
pulse. Refer to Figures 4 and 6. For an even field, the trailing
edge of VSYNC is 5±1 CLK2 cycles leading the leading edge
of the HSYNC that follows the last equalization pulse. Refer to
Figures 5 and 7.
FIELD TIMING
When field information can be determined from the input
video source, the FIELD output pin reflects the video source
8