HMP8116 Datasheet, PDF (12/43 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8116
ures 9 and 10.
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2. When BLANK
is asserted and VBIVALID is deasserted, the YCbCr outputs
have a value of 16 for Y and 128 for Cb and Cr.
CLK
DVALID
BLANK
P[15-8]
Cb₀
Y₀
Cr₀
Y₁
Cb₂
Y₂
Cr₂
Y₃
Cb₄
Y₄
NOTE:
t_DVLD
9. Y₀ is the first active luminance pixel data of a line. Cb₀ and Cr₀ are first active chrominance pixel data in a line. Cb and Cr will alternate
every cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period, but the values on the ports are forced to
blanking levels.
FIGURE 9. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 0)
CLK
DVALID
BLANK
P[15-8]
Cb₀
Y₀
Cr₀
Y₁
Cb₂
Y₂
Cr₂
Y₃
Cb₄
Y₄
NOTES:
t_DVLD
10. Y₀ is the first active luminance pixel data of a line. Cb₀ and Cr₀ are first active chrominance pixel data in a line. Cb and Cr will alternate
every cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period, but the values on the ports are forced to
blanking levels.
11. When DVLD_LTC is set to 1, the polarity of DVALID needs to be set to active low, otherwise DVALID will stay low during active video and
be gated with the clock only during the blanking interval.
FIGURE 10. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 1)
16-BIT YCbCr, 15-BIT RGB, OR 16-RGB OUTPUT
In these output modes, DVALID may be configured to oper-
ate in one of four modes as controlled by the DVLD_LTC and
DVLD_DCYC bits of the GENLOCK CONTROL register
(04_H). Bit 4 is the DVLD_LTC bit and bit 5 is the
DVLD_DCYC bit.
If DVLD_LTC=0 and DVLD_DCYC=0 , DVALID is present
only during the active video time on active scan lines. Thus,
DVALID being asserted indicates valid pixel data is present
on the P0-P15 pixel outputs. DVALID is never asserted dur-
ing the blanking intervals. In this mode DVALID will have a
50% duty cycle only during the active video times. The tim-
ing diagrams for this mode can be found in figures 11 and
12.
If DVLD_LTC=0 and DVLD_DCYC=1, DVALID behaves the
same as the first mode, with the exception that DVALID does
not have a 50% duty cycle. This mode is intended for back-
ward compatibility with HMP8112(A) timing dependancies in
which DVALID did not have a 50% duty cycle timing and
other timing variations. The timing diagrams for this mode
can be found in figures 13 and 14.
If DVLD_LTC=1 and DVLD_DCYC=0, DVALID is present the
entire line time on all scan lines. DVALID may occasionally
be negated for two consecutive CLK2 cycles just prior to
active video. In this mode DVALID is guaranteed have a 50%
duty cycle only during the active video times. The timing for
this mode differs from the timing shown in figures 11 and 12
only in that DVALID will also be asserted during the blanking
portion of the video line time as described above.
12