HMP8116 Datasheet, PDF (21/43 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8116
Host Interface
All internal registers may be written to or read by the host
processor at any time, except for those bits identified as
read-only. The bit descriptions of the control registers are
listed in Tables 8-57.
The HMP8116 supports the fast-mode (up to 400 kbps) I²C
interface consisting of the SDA and SCL pins. The device
acts as a slave for receiving and transmitting data over the
serial interface. When the interface is not active, SCL and
SDA must be pulled high using external 4kΩ pull-up resis-
tors. The slave address for the HMP8116 is 88_H.
Data is placed on the SDA line when the SCL line is low and
held stable when the SCL line is pulled high. Changing the
state of the SDA line while SCL is high will be interpreted as
either an I²C bus START or STOP condition as indicated by
Figure 19.
During I²C write cycles, the first data byte after the slave
address is treated as the control register sub address and is
written into the internal address register. Any remaining data
bytes sent during an I²C write cycle are written to the control
registers, beginning with the register specified by the
address register as given in the first byte. The address regis-
ter is then autoincremented after each additional data byte
sent on the I²C bus during a write cycle. Writes to reserved
bits within registers or reserved registers are ignored.
In order to perform a read from a specific control register
within the HMP8116, an I²C bus write must first be per-
formed to properly setup the address register. Then an I²C
bus read can be performed to read from the desired control
register(s). As a result of needing the write cycle for a read
cycle there are actually two START conditions as shown in
Figure 20. The address register is then autoincremented
after each byte read during the I²C read cycle. Reserved
registers return a value of 00_H.
t_BUF
t_SU:DATA
SDA
t_HD:DATA
SCL
t_LOW t_HIGH
t_R t_F
FIGURE 18. I²C TIMING DIAGRAM
t_SU:STOP
SDA
SCL
S
1-7
8
9
1-7
8
START
CONDITION
ADDRESS
R/W
ACK
DATA
FIGURE 19. I²C SERIAL DATA FLOW
9
ACK
P
STOP
CONDITION
DATA WRITE
1000 1000
S CHIP ADDR A
0x88
DATA READ
1000 1000 (R/W)
S CHIP ADDR A
0x88
SUB ADDR
SUB ADDR
A DATA A DATA A P
REGISTER
POINTED
TO BY
SUB ADDR
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
FROM MASTER
FROM HMP8116
AS
CHIP ADDR
0x89
A DATA
A DATA
NA P
REGISTER
POINTED
TO BY
SUB ADDR
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
FIGURE 20. REGISTER WRITE/READ FLOW
S = START CYCLE
P = STOP CYCLE
A = ACKNOWLEDGE
NA = NO ACKNOWLEDGE
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