HMP8116 Datasheet, PDF (11/43 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8116
NTSC M
PAL B, D, G, H, I, N, N_C
LINES 1 - 22 NOT ACTIVE
240 ACTIVE LINES
PER FIELD
(LINES 23-262)
480 ACTIVE
LINES / FRAME
(NTSC, PAL M) LINES 263 - 284 NOT ACTIVE
240 ACTIVE LINES
PER FIELD
(LINES 285 - 524)
LINE 525
NOT ACTIVE
TOTAL PIXELS
ACTIVE PIXELS
ODD FIELD
SYNC AND
BACK
PORCH
VERTICAL
BLANKING
EVEN FIELD
LINES 1 - 22 NOT ACTIVE
288 ACTIVE LINES
PER FIELD
(LINES 23 - 310)
LINES 311 - 335 NOT ACTIVE
576 ACTIVE
LINES / FRAME
(PAL)
FRONT
PORCH
NUMBER OF PIXELS
RECTANGULAR (SQUARE)
NTSC
PAL
858 (780)
720 (640)
864 (944)
720 (768)
288 ACTIVE LINES
PER FIELD
(LINES 336 - 623)
LINES 624-625
NOT ACTIVE
TOTAL PIXELS
ACTIVE PIXELS
NOTE:
7. The line numbering for PAL (M) followings NTSC (M) line count minus 3 per the video standards.
FIGURE 8. TYPICAL ACTIVE VIDEO REGIONS
TABLE 3. PIXEL OUTPUT FORMATS
PIN NAME
8-BIT, 4:2:2, YCbCr
16-BIT, 4:2:2, YCbCr 15-BIT, RGB, (5,5,5) 16-BIT, RGB, (5,6,5)
BT.656
P0
0 [0]
Cb0, Cr0 [D0_n+1]
B0 [D0_n+1]
B0 [D0_n+1]
0 [0]
P1
0 [0]
Cb1, Cr1 [D1_n+1]
B1 [D1_n+1]
B1 [D1_n+1]
0 [0]
P2
0 [0]
Cb2, Cr2 [D2_n+1]
B2 [D2_n+1]
B2 [D2_n+1]
0 [0]
P3
0 [0]
Cb3, Cr3 [D3_n+1]
B3 [D3_n+1]
B3 [D3_n+1]
0 [0]
P4
0 [0]
Cb4, Cr4 [D4_n+1]
B4 [D4_n+1]
B4 [D4_n+1]
0 [0]
P5
0 [0]
Cb5, Cr5 [D5_n+1]
G0 [D5_n+1]
G0 [D5_n+1]
0 [0]
P6
0 [0]
Cb6, Cr6 [D6_n+1]
G1 [D6_n+1]
G1 [D6_n+1]
0 [0]
P7
0 [0]
Cb7, Cr7 [D7_n+1]
G2 [D7_n+1]
G2 [D7_n+1]
0 [0]
P8
Y0, Cb0, Cr0 [D0]
P9
Y1, Cb1, Cr1 [D1]
P10
Y2, Cb2, Cr2 [D2]
P11
Y3, Cb3, Cr3 [D3]
P12
Y4, Cb4, Cr4 [D4]
P13
Y5, Cb5, Cr5 [D5]
P14
Y6, Cb6, Cr6 [D6]
P15
Y7, Cb7, Cr7 [D7]
Y0 [D0_n]
Y1 [D1_n]
Y2 [D2_n]
Y3 [D3_n]
Y4 [D4_n]
Y5 [D5_n]
Y6 [D6_n]
Y7 [D7_n]
G3 [D0_n]
G4 [D1_n]
R0 [D2_n]
R1 [D3_n]
R2 [D4_n]
R3 [D5_n]
R4 [D6_n]
0 [D7_n]
G3 [D0_n]
G4 [D1_n]
G5 [D2_n]
R0 [D3_n]
R1 [D4_n]
R2 [D5_n]
R3 [D6_n]
R4 [D7_n]
YCbCr Data,
Ancillary Data,
SAV and EAV
Sequences
[D0 - D7, where
P8 corresponds
to D0]
NOTE:
8. Definitions in brackets are port definitions during raw VBI data transfers. Refer to the section on teletext for more information on raw VBI.
PIXEL OUTPUT PORT
Pixel data is output via the P0-P15 pins. Refer to Table 3 for
the output pin definition as a function of the output mode.
8-BIT YCbCr OUTPUT
The DVALID output pin may be configured to operate in one
of two ways. The configuration is determined by the
DVLD_LTC bit (bit 4) of the GENLOCK CONTROL register
04_H.
If DVLD_LTC=0, the DVALID output is continuously asserted
during the entire active video time on active scan lines if CLK2
is exactly 2x the desired output sample rate. DVALID being
asserted indicates valid pixel data is present on the P15-P8
pixel outputs. DVALID is never asserted during the blanking
intervals. Refer to Figure 9.
If DLVD_LTC=1, DVALID has the same internal timing as the
first mode, but is ANDed with the CLK2 signal, and the result
is output onto the DVALID pin. This results in a gated CLK2
signal being output during the active video time on active
scan lines. Refer to Figure 10.
If 8-bit YCbCr data is generated, it is output following each
rising edge of CLK2. The YCbCr data is multiplexed as [Cb Y
Cr Y′ Cb Y Cr Y′...], with the first active data each scan line
containing Cb data. The pixel output timing is shown in Fig-
11