HMP8116 Datasheet, PDF (34/43 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8116
BIT
NO.
FUNCTION
7-6
Reserved
5-0
Sharpness
Adjust
BIT
NO.
FUNCTION
7
Software Reset
6
Power Down
5
Closed Caption
Odd Field
Read Status
4
Closed Caption
Even Field
Read Status
3
WSS
Odd Field
Read Status
2
WSS
Even Field
Read Status
1-0
Reserved
BIT
NO.
FUNCTION
7-0
Odd Field
Caption Data
BIT
NO.
15-8
FUNCTION
Odd Field
Caption Data
TABLE 37. SHARPNESS REGISTER
SUB ADDRESS = 1E_H
DESCRIPTION
RESET
STATE
These bits control the amount of gain control of high frequency luminance signals (either
2.6MHz or Fsc). They may have a value of +12dB (“11 1111”) to -12dB (“00 0100”). A val-
ue of 0dB (“01 0000”) has no effect on the data. This register is ignored if the sharpness
mode selection is “disable sharpness control” or “reserved”.
00_B
010000_B
TABLE 38. HOST CONTROL REGISTER
SUB ADDRESS = 1F_H
DESCRIPTION
When this bit is set to 1, the entire device except the I²C bus is reset to a known state
exactly like the RESET input going active. The software reset will initialize all register bits
to their reset state. Once set this bit is self clearing. This bit is cleared on power-up by the
external RESET pin.
When this bit is set to a 1, the entire device is shut down except the I²C bus by gating off
the clock. For normal decoding operations this bit should be set to a 0.
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the caption
data has been read out via the I²C interface or as BT.656 ancillary data.
0 = No new caption data
1 = Caption_ODD_A and Caption_ODD_B data registers contain new data.
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the caption
data has been read out via the I²C interface or as BT.656 ancillary data.
0 = No new caption data
1 = Caption_EVEN_A and Caption_EVEN_B data registers contain new data.
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the WSS
data has been read out via the I²C interface or as BT.656 ancillary data.
0 = No new WSS data
1 = WSS_ODD_A and WSS_ODD_B data registers contain new data.
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the WSS
data has been read out via the I²C interface or as BT.656 ancillary data.
0 = No new WSS data
1 = WSS_EVEN_A and WSS_EVEN_B data registers contain new data.
TABLE 39. CLOSED CAPTION_ODD_A DATA REGISTER
SUB ADDRESS = 20_H
DESCRIPTION
If odd field captioning is enabled and present, this register is loaded with the first eight bits
of caption data on line 18, 21, or 22. Bit 0 corresponds to the first bit of caption information.
Data written to this register is ignored.
RESET
STATE
0_B
0_B
0_B
0_B
0_B
0_B
00_B
RESET
STATE
80_H
TABLE 40. CLOSED CAPTION_ODD_B DATA REGISTER
SUB ADDRESS = 21_H
DESCRIPTION
If odd field captioning is enabled and present, this register is loaded with the second eight
bits of caption data on line 18, 21, or 22. Data written to this register is ignored.
RESET
STATE
80_H
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