HMP8116 Datasheet, PDF (39/43 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8116
power plane. The analog power plane should be connected
to the board’s normal V_CC power plane at a single point
though a low-resistance ferrite bead, such as a Ferroxcube
5659065-3B, Fair-Rite 2743001111, or TDK BF45-4001. The
ferrite bead provides resistance to switching currents,
improving the performance of HMP8116. A single 47µF
capacitor should also be used between the analog power
plane and the ground plane to control low-frequency power
supply ripple.
If a separate linear regulator is used to provide power to the
analog power plane, the power-up sequence should be
designed to ensure latchup will not occur. A separate linear reg-
ulator is recommended if the power supply noise on the V_AA
pins exceeds 200mV.
Analog Signals
Traces containing digital signals should not be routed over,
under, or adjacent to the analog output traces to minimize
crosstalk. If this is not possible, coupling can be minimized
by routing the digital signals at a 90 degree angle to the ana-
log signals. The analog input traces should also not overlay
the V_AA power plane to maximize high-frequency power sup-
ply rejection.
EVALUATION BOARD
HMPVIDEVAL/ISA
The HMPVIDEVAL/ISA evaluation board allows connecting
the HMP8116 into a PC ISA slot for evaluation. It includes
the HMP8115 NTSC/PAL decoder, 3MB of VRAM, and a
NTSC/PAL encoder. The board accepts composite or S-
video input and displays video on a standard TV. The ISA
bus and evaluation software allow easy performance evalua-
tion of the HMP8116 using tools such as the Tektronix
VM700 video test system.
RELATED APPLICATION NOTES
Application Notes are also available on the Harris Multime-
dia web site at http://www.semi.harris.com/mmedia.
AN9644: Composite Video Separation Techniques
AN9716: Widescreen Signalling
AN9717: YCbCr to RGB Considerations
AN9728: BT.656 Video Interface for ICs
AN9738: VMI Video Interface for ICs
CVBS1
CVBS2
CVBS3/Y
R3
75
CHROMA
R4
75
U1
R2 R1
75 75
C4
1.0µF
C1 7
1.0µF ^{CVBS 1}
C2 6
1.0µF ^{CVBS 2}
C3 5 _{CVBS 3 (Y)}
1.0µF
ANTI-ALIAS
FILTER
19 _C
HMP8116
ANTI-ALIAS
FILTER
8 _YIN
P7 ⁵¹
P6 ⁵⁰
P5 ⁴⁹
P4 ⁴⁸
P3 ⁴⁷
P2 ⁴⁵
P1 ⁴³
P0 ⁴²
P15
P14
P13
P12
P11
P10
P9
P8
64
63
60
58
57
56
55
54
C6
0.1µF
C7
0.1µF
9 _YOUT
76 _LCAP
29 _CCAP
BLANK ⁶⁵
DVALID ⁶⁶
FIELD ⁶⁷
HSYNC ⁷¹
VSYNC ⁷⁰
VBIVALID ⁶¹
INTREQ ⁴⁴
C8
1.0µF
R6
12K
78 _{REF_CAP}
28 _RSET
RESET ³⁴
SDA ⁴⁰
41
SCL
38
CLK2
P[7..0]
P[15..8]
V_CC
V_CC V_CC
R16 R17
RP1 4K 4K
10K
BLANK
DVALID
FIELD
HSYNC
VSYNC
VBIVALID
INTREQ
RESET
27MHz
R8
50
C12
15pF
27MHz
SDA
SCL
FIGURE 21. HMP8116 REFERENCE SCHEMATICS
39