HMP8116 Datasheet, PDF(13/43 Page) Intersil Corporation

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HMP8116 Datasheet, PDF (13/43 Pages) Intersil Corporation – NTSC/PAL Video Decoder

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HMP8116

If DVLD_LTC=1 and DVLD_DCYC=1, DVALID is present

during the entire line time on all scan lines. DVALID is

asserted during the blanking intervals as needed to ensure a

constant number of total samples per line. The timing for this

mode differs from the timing shown in ï¬gures 13 and 14 only

in that DVALID will also be asserted during the blanking por-

tion of the video line time as described above.

If 16-bit YCbCr, 15-bit RGB data, or 16-bit RGB data is gen-

erated, it is output following the rising edge of CLK2 while

DVALID is asserted. Either linear or gamma-corrected RGB

data may be output. The pixel output timing is shown in Fig-

ures 11 to 14.

BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD

are output following the rising edge of CLK2. When BLANK

is asserted and VBIVALID is deasserted, the YCbCr outputs

have a value of 16 for Y and 128 for Cb and Cr; the RGB out-

puts have a value of 0.

CLK

DVALID

BLANK

P15-P8

P7-P0

Cb0

Cr0

Cb2

Cr2

Cb4

NOTES:

tDVLD

12. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate

every cycle due to the 4:2:2 subsampling.

13. BLANK is asserted per Figure 8.

FIGURE 11. OUTPUT TIMING FOR 16-BIT YCbCr MODE (DVLD_LTC = 0, DVLD_DCYC = 0)

CLK

DVALID

P15-P11

[P14-P10]

P10-P5

[P9-P5]

P4-P0

NOTE:

tDVLD

14. BLANK is asserted per Figure 8.

FIGURE 12. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 0)

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