HMP8116 Datasheet, PDF (36/43 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8116
BIT
NO.
15-14
13-8
FUNCTION
Reserved
Even Field
WSS Data
BIT
NO.
FUNCTION
7-6
Reserved
5-0
Even Field
WSS CRC Data
BIT
NO.
FUNCTION
7-0
Assert BLANK
Output Signal
BIT
NO.
15-10
9-8
FUNCTION
Reserved
Assert BLANK
Output Signal
BIT
NO.
FUNCTION
7-0
Negate BLANK
Output Signal
BIT
NO.
FUNCTION
7-0
Assert BLANK
Output Signal
TABLE 48. WSS_EVEN_B DATA REGISTER
SUB ADDRESS = 28_H
DESCRIPTION
If even field WSS is enabled and present, this register is loaded with the second six bits
of WSS information on line 280, 283, or 336. Data written to this register is ignored.
RESET
STATE
00_B
000000_B
TABLE 49. WSS_CRC_EVEN DATA REGISTER
SUB ADDRESS = 29_H
DESCRIPTION
RESET
STATE
If even field WSS is enabled and present during NTSC operation, this register is loaded
with the six bits of CRC information on line 283. It is always a “000000” during PAL oper-
ation. Data written to this register is ignored.
00_B
000000_B
TABLE 50. START H_BLANK LOW REGISTER
SUB ADDRESS = 30_H
DESCRIPTION
This 8-bit register is cascaded with Start H_Blank High Register to form a 10-bit
start_horizontal_blank REGISTER. It specifies the horizontal count (in 1x clock cycles) at
which to assert BLANK each scan line. Bit 0 is always a “0”, so the start of horizontal
blanking may only be done with two pixel resolution. The leading edge of HSYNC is count
000_H.
TABLE 51. START H_BLANK HIGH REGISTER
SUB ADDRESS = 31_H
DESCRIPTION
This 2-bit register is cascaded with Start H_Blank Low Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at
which to assert BLANK each scan line. The leading edge of HSYNC is count 000_H.
TABLE 52. END H_BLANK REGISTER
SUB ADDRESS = 32_H
DESCRIPTION
This 8-bit register specifies the horizontal count (in 1x clock cycles) at which to negate
BLANKeach scan line. Bit 0 is always a “0”, so the end of horizontal blanking may only be
done with two pixel resolution. The leading edge of HSYNC is count 000_H.
TABLE 53. START V_BLANK LOW REGISTER
SUB ADDRESS = 33_H
DESCRIPTION
This 8-bit register is cascaded with Start V_Blank High Register to form a 9-bit
start_vertical_blank register. It specifies the line number to assert BLANK each field.
For NTSC operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even
fields. For PAL operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even
fields.
RESET
STATE
4A_H
RESET
STATE
000000_B
11_B
RESET
STATE
7A_H
RESET
STATE
02_H
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