HMP8116 Datasheet, PDF (42/43 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8116
Electrical Specifications V_CC = V_AA = 5.0V, T_A = 25^oC (Continued)
PARAMETER
Luminance Nonlinearity
SYMBOL
TEST CONDITION
NTC-7 Composite (Note 2)
MIN
TYP
MAX UNITS
-
2
-
%
SNR
GENLOCK PERFORMANCE
SNRL _WEIGHTED Pedestal Input (Note 2)
-
50
-
dB
Horizontal Locking Time
t_LOCK
Time from Initial Lock
Acquisition to an Error of
1 Pixel. (Note 2)
2
3
-
Fields
Long-Term horizontal Sync
Lock Range
Range over specified pixel jitter
-
-
is maintained. Assumes line
time changes by amount indicat-
ed slowly between over one
field. (Note 2)
5
%
Number of Missing Horizontal
Syncs
Before Lost Lock Declared
H_{SYNC LOST}
Programmable via register 04_H 1 or 12
(Note 2)
1 or 12
1 or 12 Hsyncs
Number of Missing Vertical Syncs
Before Lost Lock Declared
V_{SYNC LOST}
1 or 3
1 or 3
1 or 3 Vsyncs
Long-Term Color Subcarrier
Lock Range
Range over color subcarrier
-
locking time and accuracy spec-
ifications are maintained. Sub-
carrier frequency changes by
amount indicated slowly over 24
hours. (Note 2)
±200
±400
Hz
Vertical Sample Alignment
(Notes 2, 4)
-
1/8
-
Pixel
-
10
-
ns
NOTES:
2. Guaranteed by design or characterization.
3. Test performed with C_L = 40pF, I_OL = 4mA, I_OH = -4mA. Input reference level is 1.5V for all inputs. V_IH = 3.0V, V_IL = 0V.
4. This should not be confused with Clock Jitter, since the HMP8116 does not generate the sample clock. Thus, clock jitter is solely depen-
dent on the source of the CLK2 signal. The Vertical Sample Alignment parameter specifies how accurately samples align vertically from
one scan line to the next.
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