HMP8116 Datasheet, PDF (31/43 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8116
TABLE 23. INTERRUPT STATUS REGISTER
BIT
NO.
FUNCTION
SUB ADDRESS = 10_H
DESCRIPTION
RESET
STATE
7
Genlock Loss
If this bit is a “1”, the reason for the interrupt request was that genlock was lost. To clear
0_B
Interrupt Status
the interrupt request, a “1” must be written to this bit.
6
Input Signal Loss If this bit is a “1”, the reason for the interrupt request was that the input video source is no
0_B
Interrupt Status
longer present. To clear the interrupt request, a “1” must be written to this bit.
5
Closed Caption
If this bit is a “1”, the reason for the interrupt request was that the Caption_ODD_A and
0_B
Interrupt Status
Caption_ODD_B or the Caption_EVEN_A and Caption_EVEN_B data registers contain
new data. To clear the interrupt request, a “1” must be written to this bit.
4
WSS
If this bit is a “1”, the reason for the interrupt request was that the WSS_ODD_A and
0_B
Interrupt Status
WSS_ODD_B or the WSS_EVEN_A and WSS_EVEN_B data registers contain new data.
To clear the interrupt request, a “1” must be written to this bit.
3
Teletext
If this bit is a “1”, the reason for the interrupt request was that teletext data has been de-
0_B
Interrupt Status
tected in the current field. To clear the interrupt request, a “1” must be written to this bit.
2
Reserved
0_B
1
Auto Detect
If this bit is a “1”, the reason for the interrupt request was that the video standard has been
0_B
Video Standard
automatically determined. To clear the interrupt request, a “1” must be written to this bit.
Interrupt Status
0
Vertical Sync
If this bit is a “1”, the reason for the interrupt request was that a new field was started. To
0_B
Interrupt Status
clear the interrupt request, a “1” must be written to this bit.
TABLE 24. RAW VBI CONTROL REGISTER
BIT
NO.
FUNCTION
SUB ADDRESS = 11_H
DESCRIPTION
RESET
STATE
7-4
Reserved
0000_B
3
RAW Preamble En- If this bit is a “1”, the RAW VBI data stream will have a preamble consisting of four bytes.
0_B
able
Which are FF_H, CNT1, CNT2 and 00H. Where CNT1 = even parity bar, even parity[5-0],
0, Field (0=Odd, 1=Even), linecount[8-4] and CNT2 = even parity bar, even parity [5-
0],0,0,linecount[3-0].
2
RAW VBI All
If this bit is a “1”, all the video lines excluding the lines used for equalization and serration
0_B
pulses are converted to RAW VBI data.
If this bit is a “0”, only the lines enbled in the RAW VBI LINE MASK registers are converted
to RAW VBI data.
1
RAW VBI Even
If this bit is a “1”, the even field lines are converted to RAW VBI data as specified by the
0_B
Field
RAW VBI All bit and the RAW VBI Line Mask registers.
If this bit is a “0”, the even field lines are not included in the lines to be converted to RAW
VBI data.
0
RAW VBI Odd Field If this bit is a “1”, the odd field lines are converted to RAW VBI data as specified by the
0_B
RAW VBI All bit and the RAW VBI Line Mask registers.
If this bit is a “0”, the odd field lines are not included in the lines to be converted to RAW
VBI data.
TABLE 25. RAW VBI START COUNT REGISTER
BIT
NO.
FUNCTION
SUB ADDRESS = 12_H
DESCRIPTION
RESET
STATE
7-0
Raw VBI Start
Count
Specifies where to start generating raw VBI data in two sample clock steps from the 50%
7A_H
point of the leading edge of HSYNC.
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