HMP8116 Datasheet, PDF (26/43 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8116
TABLE 14. GENLOCK CONTROL REGISTER
BIT
NO.
FUNCTION
SUB ADDRESS = 04_H
DESCRIPTION
RESET
STATE
7
Aspect Ratio
0 = Rectangular (BT.601) pixels
0_B
Mode
1 = Square pixels
6
Freeze Output
Setting this bit to a “1” freezes the output timing at the end of the field. Resetting this bit
0_B
Timing Enable
to a “0” resumes normal operation at the start of the next field.
0 = Normal operation
1 = Freeze output timing
5
DVALID Duty Cycle This bit is ignored during the 8-bit YCbCr and BT.656 output modes.
0_B
Control
During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
(DVLD_DCYC)
0 = DVALID has 50/50 duty cycle at the pixel output datarate
1 = DVALID goes active based on linelock. This will cause DVALID to not have a 50/50
duty cycle. This bit is intended to be used in maintaining backward compatibilty with the
HMP8112A DVALID output timing.
4
DVALID Line Timing During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
0_B
Control
0 = DVALID present only during active video time on active scan lines
(DVLD_LTC)
1 = DVALID present the entire scan line time on all scan lines
During the 8-bit YCbCr and BT.656 output modes, this bit defines the DVALID output sig-
nal as:
0 = Normal timing
1 = DVALID signal ANDed with CLK2
3
Missing HSYNC
This bit specifies the number of missing horizontal sync pulses before the device goes into
0_B
Detect Select
the horizontal lock acquisition mode. In mode “0”, the default value of the HPLL Adjust
register should be used. In mode “1”, the typical values the HPLL Adjust register should
be 10_H to 20_H.
0 = 12 pulses
1 = 1 pulse
2
Missing VSYNC
This bit specifies the number of missing vertical sync pulses before the device goes into
0_B
Detect Select
the vertical lock acquisition mode.
0 = 3 pulses
1 = 1 pulse
1-0
CLK2 Frequency This bit indicates the frequency of the CLK2 input clock.
01_B
00 = 24.54MHz
01 = 27.0MHz
10 = 29.5MHz
11 = Reserved
26