PD6710 Datasheet, PDF (93/138 Pages) Intel Corporation – ISA-to-PC-Card (PCMCIA) Controllers

ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
13.2
Example Implementations of GPSTB-Controlled Read and
Write Ports
Figure 13. Example GPSTB Write Port (Extension Control 2 bits 4:3 are ‘10’)
IOW*
SD[15:0]
(16-bit bus)
PWRGOOD
PD6722
IOW*
SD[15:0]
GPSTB
Pull-up^†
EXT_WR*
Latch
(for example, ’374)
CK ^O7
SD[15:8]
D
O0
General-
Purpose
Outputs
RES
† _{Pull-up resistor, or set Extension Control 2 bit 2 to ‘1’ for totem-pole output.}
In this mode, Extension Control 2 register bit 4 is set to ‘1’ enabling the GPSTB pin to function as
a write strobe. Writes to the respective extended index 0Ah cause the respective GPSTB to go
active (low) for the duration of the system’s IOW* pulse.
On writes, data is written to both the external latch and the internal shadow copy of the External
Data register. A read of the respective extended index 0Ah would produce the last value written to
the latch.
Connection of the ISA bus PWRGOOD signal to the external latch ensures that the latch assumes
all ‘0’s at its outputs when the PD67XX is reset.
Figure 14. Example GPSTB Read Port (Extension Control 2 bits 4:3 are ‘01’)
IOR*
SD[15:0]
(16-bit bus)
PD6722
IOR*
SD[15:0]
GPSTB
EXT_RD*
General-
Purpose
Pull-up^{† Inputs}
Tristate Buffer
(for example, ’244)
D7
SD[15:8]
O
D0
OE
† _{Pull-up resistor, or set Extension Control 2 bit 2 to ‘1’ for totem-pole output.}
Datasheet
93