PD6710 Datasheet, PDF (104/138 Pages) Intel Corporation – ISA-to-PC-Card (PCMCIA) Controllers

PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
16.3
AC Timing Specifications
This section includes system timing requirements for the PD67XX. Timings are provided in
nanoseconds (ns), at TTL input levels, with the ambient temperature varying from 0°C to 70°C,
and V_CC varying from 3.0 to 3.6 V or 4.5 to 5.5 V DC. The AT bus speed is 10 MHz unless
otherwise noted. Note that an asterisk (*) denotes an active-low signal for the ISA bus interface,
and a dash (-) denotes an active-low signal for the PC Card socket interface.
• Additionally, the following statements are true for all timing information:
• All timings assume a load of 50 pF.
• TTL signals are measured at TTL threshold; CMOS signals are measured at CMOS threshold.
Table 25. List of AC Timing Specifications
Title
Table 26 “ISA Bus Timing”
Table 27 “Reset Timing”
Table 28 “Pulse Mode Interrupt Timing”
Table 29“General-Purpose Strobe Timing”
Table 30 “Input Clock Specification”
Table 31 “Memory Read/Write Timing (Word Access)”
Table 32 “Word I/O Read/Write Timing”
Table 33 “PC Card Read/Write Timing when System Is 8-Bit”
Table 34 “Normal Byte Read/Write Timing”
Table 35 “16-Bit System to 8-Bit I/O Card: Odd Byte Timing”
Table 36 “DMA Read Cycle Timing (PD6722 only)”
Table 37 “DMA Write Cycle Timing (PD6722 only)”
Table 38 “DMA Request Timing (PD6722 only)”
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16.4
ISA Bus Timing
Table 26. ISA Bus Timing (Sheet 1 of 2)
Symbol
Parameter
MIN
MAX
Unit
t₁
MEMCS16* active delay from LA[23:17] valid
40
ns
t_1a
LA[23:17] setup to ALE inactive
30
ns
t_1b
LA[23:17] hold from ALE inactive
t₂
IOCS16* active delay from SA[15:0]¹
5
ns
40
ns
1. AEN must be inactive for t₂, t₃, and t₆ timing specifications to be applicable.
2. Command is defined as IOR*, IOW*, MEMR*, or MEMW*.
3. Except for valid card memory writes, which are zero wait state when internal write FIFO is not full.
4. If card is removed during a card access cycle, IOCHRDY is three-stated without waiting for end of Command.
5. Based on 25-MHz internal clock, produced either by an internal synthesizer and 14.318-MHz signal applied to CLK pin, or by
supplying 25 MHz directly to CLK pin and bypassing the internal synthesizer.
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Datasheet