PD6710 Datasheet, PDF (117/138 Pages) Intel Corporation – ISA-to-PC-Card (PCMCIA) Controllers

ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 36. DMA Read Cycle Timing (PD6722 only) (Sheet 2 of 2)
Symbol
Parameter
MIN
MAX
Units
t₇
System TC (-VPP_VALID high) to -IOWR
t₈
-IOWR to begin of card TC (-WE)⁴
t₉
End of card TC (-WE) to -IOWR inactive⁴
−40
ns
25
50
ns
25
50
ns
1. The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer Set
0 default value of 01h, the setup time would be 70 ns. S = (N_pres × N_val + 1), see “PC Card Bus Timing Calculations” on
page 109.
2. The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (N_pres × N_val + 1), see page 109.
3. The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (N_pres × N_val + 1), see page 109.
4. Based on an internal clock period of 40 ns (25 MHz).
Figure 28. DMA Read Cycle Timing
IRQ10
(DRQ)
IRQ9
(DACK*)
t₁
-IORD, -OE
(high)
-REG
(DACK* to card)
-CE[2:1]
t₂
t₃
t₄
-IOWR
-WAIT
t₅
t₆
DMA DATA[15:0]
to card
t₇
-VPP_VALID
(TC from system)
t₈
t₉
-WE
(TC to card)
Datasheet
117