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PD6710 Datasheet, PDF (108/138 Pages) Intel Corporation – ISA-to-PC-Card (PCMCIA) Controllers
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PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Figure 20. Pulse Mode Interrupt Timing
IRQ[XX]
High-Z
t1
t1
High-Z
High-Z = high impedance
NOTE: Each time indicated is 2 clock periods of the CLK input to the PD67XX, independent of setting of the
Bypass Frequency Synthesizer bit.
16.4.3
General-Purpose Strobe Timing (PD6722 only)
Table 29. General-Purpose Strobe Timing
Symbol
Parameter
t1
GPSTB delay after IOR* or IOW* active
t2
GPSTB delay after IOR* or IOW* inactive
Figure 21. General-Purpose Strobe Timing
t1
IOR*, IOW*
MIN
MAX
Units
40
ns
40
ns
t2
GPSTB
16.4.4
Input Clock Specification
Table 30. Input Clock Specification (Sheet 1 of 2)
Symbol
Parameter
MIN
MAX
t1
t2
t3
t4
Vcenter
CLK pin input rise time
CLK pin input fall time
CLK input low period
CLK input high period
Center voltage at which period
specified
1
1
0.4 TCLKP
0.4 TCLKP
0.5 VDD
7
7
0.6 TCLKP
0.6 TCLKP
0.5 VDD
Units
ns
ns
ns
ns
V
Conditions
108
Datasheet
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