PD6710 Datasheet, PDF (116/138 Pages) Intel Corporation – ISA-to-PC-Card (PCMCIA) Controllers

PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Figure 27. 16-Bit System to 8-Bit I/O Card: Odd Byte Timing
-REG,
A[25:0]
t₁
-IOIS16
t₂
-CE2
t₃
-CE1
t₄
t₅
t₆
-IOWR, -IORD
D[7:0]
Write Cycle
D[7:0]
Read Cycle
D[15:8]
Read or
Write Cycle
Odd Data
XX
Odd Data
Table 36. DMA Read Cycle Timing (PD6722 only) (Sheet 1 of 2)
Symbol
Parameter
MIN
MAX
Units
t₁
DRQ (IRQ10) and DACK* (IRQ9) active to DMA cycle begin
40
ns
t₂
-CE[2:1], -REG, -IORD, -OE, and Write Data setup to -IOWR
active¹
(S × Tcp) – 10
ns
t₃
Command: -IOWR pulse width²
(C × Tcp) – 10
ns
t₄
Recovery: -IOWR inactive to end of cycle³
(R × Tcp) – 10
ns
t₅
-WAIT active from -IOWR active
(C – 2)Tcp – 10
ns
t₆
-WAIT inactive to -IOWR inactive
2 Tcp
ns
1. The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer Set
0 default value of 01h, the setup time would be 70 ns. S = (N_pres × N_val + 1), see “PC Card Bus Timing Calculations” on
page 109.
2. The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (N_pres × N_val + 1), see page 109.
3. The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (N_pres × N_val + 1), see page 109.
4. Based on an internal clock period of 40 ns (25 MHz).
116
Datasheet