PD6710 Datasheet, PDF (105/138 Pages) Intel Corporation – ISA-to-PC-Card (PCMCIA) Controllers

ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 26. ISA Bus Timing (Sheet 2 of 2)
Symbol
Parameter
MIN
MAX
Unit
t_2a
IOCS16* inactive delay from SA[15:0]¹
SA[16:0], SBHE* setup to any Command active^{1, 2}
t₃
LA[23:17] latching by ALE to any Command active
t₄
Any Command active to IOCHRDY inactive (low)³
t_4a
IOCHRDY three-state from Command inactive⁴
t₅
MEMCS16* inactive delay from unlatched LA[23:17]
t_6a
IOW* or IOR* pulse width¹
t_6b
MEMW* or MEMR* pulse width¹
t₇
Any Command inactive to next Command active
t₈
Address or SBHE* hold from any Command inactive
Data valid from MEMW* active⁵
t₉
Data valid from IOW* active
40
ns
30
ns
90
ns
40
ns
5
30
40
ns
140
ns
180
ns
100
ns
0
ns
40
ns
40
ns
Data hold from MEMW* inactive
t₁₀
Data hold from IOW* inactive
5
ns
5
ns
t₁₁
Data delay from IOR* active, for internal registers
0
130
ns
t₁₂
Data delay from IOCHRDY active
15
ns
t₁₃
Data hold from IOR* or MEMR* inactive
0
30
ns
t₁₄
AEN inactive setup to valid IOR* or IOW* active
40
ns
t₁₅
AEN hold from IOR* or IOW* inactive
5
ns
t₁₆
REFRESH* inactive setup to valid MEMR* or MEMW* active
40
ns
t₁₇
REFRESH* inactive hold from MEMR* or MEMW* active
0
ns
t₁₈
MEMCS16* active delay from SA[16:12] valid
40
ns
t₁₉
*ZWS delay from MEMW* active
30
ns
t₂₀
*ZWS hold from MEMW* inactive
15
ns
1. AEN must be inactive for t₂, t₃, and t₆ timing specifications to be applicable.
2. Command is defined as IOR*, IOW*, MEMR*, or MEMW*.
3. Except for valid card memory writes, which are zero wait state when internal write FIFO is not full.
4. If card is removed during a card access cycle, IOCHRDY is three-stated without waiting for end of Command.
5. Based on 25-MHz internal clock, produced either by an internal synthesizer and 14.318-MHz signal applied to CLK pin, or by
supplying 25 MHz directly to CLK pin and bypassing the internal synthesizer.
Datasheet
105